Allow specifying of clock for blackbox module

src/main/scala/BlackBox.scala

@@ -90,7 +90,7 @@ class VerilogParameters {
   * // Implement functionality of DSP to allow simulation verification
   * } }}}
   */
-abstract class BlackBox extends Module {
+abstract class BlackBox( bbClock: Option[Clock] = None, bbReset: Option[Bool] = None) extends Module( bbClock, bbReset ) {
   Driver.blackboxes += this
   private val clockMapping = new HashMap[String, String]
 

src/test/resources/BlackBoxSuite_UserMod_1.v

@@ -0,0 +1,15 @@
+module BlackBoxSuite_UserMod_1(
+    input [3:0] io_in,
+    output[3:0] io_out
+);
+
+  wire[3:0] userbb_out;
+
+
+  assign io_out = userbb_out;
+  UserBB userbb(
+       .in( io_in ),
+       .out( userbb_out )
+  );
+endmodule
+

src/test/resources/BlackBoxSuite_UserMod_2.v

@@ -0,0 +1,35 @@
+module BlackBoxSuite_UserMod_2(input clk, input usrClk, input reset,
+    input [3:0] io_in,
+    output[3:0] io_out
+);
+
+  reg [3:0] inDelay;
+  wire[3:0] T0;
+  wire[3:0] userbb_out;
+
+`ifndef SYNTHESIS
+// synthesis translate_off
+  integer initvar;
+  initial begin
+    #0.002;
+    inDelay = {1{$random}};
+  end
+// synthesis translate_on
+`endif
+
+  assign T0 = reset ? 4'h0 : io_in;
+  assign io_out = userbb_out;
+  UserClockedBB userbb(.clkIn(usrClk), .rst(reset),
+       .in( inDelay ),
+       .out( userbb_out )
+  );
+
+  always @(posedge clk) begin
+    if(reset) begin
+      inDelay <= 4'h0;
+    end else begin
+      inDelay <= io_in;
+    end
+  end
+endmodule
+

src/test/scala/BlackBoxSuite.scala

@@ -0,0 +1,72 @@
+
+import org.junit.Assert._
+import org.junit.Test
+import org.junit.Ignore
+
+import Chisel._
+
+class BlackBoxSuite extends TestSuite {
+
+  class UserBB extends BlackBox {
+    val io = new Bundle {
+      val in = UInt( INPUT, 4 )
+      val out = UInt( OUTPUT, 4 )
+    }
+    io.in.setName("in")
+    io.out.setName("out")
+    setModuleName("UserBB")
+    io.out := io.in
+  }
+
+  class UserClockedBB( clkIn : Clock ) extends BlackBox( bbClock = clkIn ) {
+    val io = new Bundle {
+      val in = UInt( INPUT, 4 )
+      val out = UInt( OUTPUT, 4 )
+    }
+    io.in.setName("in")
+    io.out.setName("out")
+    setModuleName("UserClockedBB")
+    io.out := Reg( init = UInt(0, 4), next = io.in )
+    renameClock( clkIn, "clkIn" )
+    renameReset("rst")
+  }
+
+  @Test def userBBTest {
+
+    class UserMod extends Module {
+      val io = new Bundle {
+        val in = UInt( INPUT, 4 )
+        val out = UInt( OUTPUT, 4 )
+      }
+      val userbb = Module( new UserBB )
+      userbb.io <> io
+    }
+
+    chiselMain(Array[String]("--backend", "v",
+      "--targetDir", dir.getPath.toString()),
+      () => Module(new UserMod))
+    assertFile("BlackBoxSuite_UserMod_1.v")
+  }
+
+  @Test def userClockedBBTest {
+
+    class UserMod extends Module {
+      val io = new Bundle {
+        val in = UInt( INPUT, 4 )
+        val out = UInt( OUTPUT, 4 )
+      }
+      val inDelay = Reg( init = UInt( 0, 4 ), next = io.in )
+      val usrClk = Clock( src = clock, period = 2 )
+      usrClk.setName("usrClk")
+      val userbb = Module( new UserClockedBB( usrClk ) )
+      userbb.io.in := inDelay
+      io.out := userbb.io.out
+    }
+
+    chiselMain(Array[String]("--backend", "v",
+      "--targetDir", dir.getPath.toString()),
+      () => Module(new UserMod))
+    assertFile("BlackBoxSuite_UserMod_2.v")
+  }
+
+}