Conditional Assignments and Memories tutorial issue

[barabanshek]

Hi, I think there is an issue in this tutorial in the line "val read_port1 = UInt(32.W)". Should it be "val read_port1 = Wire(UInt(32.W))"? Because UInt is a bare Chisel type and the following exception takes a place: "ExpectedHardwareException ... must be hardware, not a bare Chisel type" if just UInt is used.

[chick]

I'm sorry but I can't seem to find which file this occurs in can you provide that.

[ucbjrl]

I stumbled over this as well. It's in the "Conditional Assignments and Memories <https://github.com/ucb-bar/chisel-tutorial/wiki/Conditional-Assignments-and-Memories>" section of the chisel-tutorial wiki.

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On Wed, Mar 28, 2018 at 2:47 PM, Chick Markley ***@***.***> wrote: I'm sorry but I can't seem to find which file this occurs in can you provide that. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#120 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AGh1wH4MjotATsft1TtxC-rOpefQWXUlks5tjAT0gaJpZM4S_Ilq> .