Merge pull request #134 from ucb-bar/intermediate-dump-vlog

Dump per macro verilog (overridden by final verilog output)
ucb-bar · Oct 16, 2023 · 60a1be9 · 60a1be9
2 parents 887c1c9 + eef5efb
commit 60a1be9
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/src/main/scala/barstools/macros/MacroCompiler.scala b/src/main/scala/barstools/macros/MacroCompiler.scala
@@ -911,6 +911,7 @@ object MacroCompiler extends App {
               .execute(
                 Array.empty,
                 Seq(
+                  OutputFileAnnotation(params.get(Verilog).get),
                   RunFirrtlTransformAnnotation(new VerilogEmitter),
                   EmitCircuitAnnotation(classOf[VerilogEmitter]),
                   FirrtlSourceAnnotation(circuit.serialize)
@@ -922,6 +923,7 @@ object MacroCompiler extends App {
               .value
           }
           .mkString("\n")
+
         val verilogWriter = new FileWriter(new File(params.get(Verilog).get))
         verilogWriter.write(verilog)
         verilogWriter.close()