feat: TQ3 compressed ring all-reduce for TP bandwidth reduction

[influenist]

Summary

Adds optional TQ3 compression to the Native TP backend's ring all-reduce, reducing inter-GPU data transfer by ~6.4x (fp16 → 2.5 bits/value).

Independent of PR #180 — this is a communication optimization, not a quantization format.

How it works

Each ring iteration:

1. Compress: fp16 → TQ3 (10 bytes per 32 values) before writing to shared memory
2. Decompress+accumulate: fused read+decode+add from predecessor's slot
3. Broadcast: forward accumulated result (uncompressed)

When it helps

Interconnect	Bandwidth	TQ3 benefit
PCIe Gen4 x16	32 GB/s	Significant — ~6x less data
InfiniBand HDR	25 GB/s	Large — network is bottleneck
Ethernet 100G	12.5 GB/s	Essential
NVLink (A100+)	600+ GB/s	Minimal — compute dominates

Files (7 files, +694 lines)

• `parallel/tq3_compress.cuh` — thread-level compress/decompress/decompress+add primitives
• `parallel/tq3_all_reduce.cu/.cuh` — compressed ring kernel using existing ParallelContext
• `bindings.cpp` — `ext.tq3_all_reduce()` binding
• `model_tp_backend.py` — `TPBackendNative.tq3_compress` opt-in flag
• `tests/test_tq3_allreduce.py` — 7 simulation tests (no multi-GPU needed)
• `tests/bench_tq3_allreduce.py` — bandwidth break-even analysis

Opt-in

backend.tq3_compress = True  # Enable compressed communication

Test plan

• `pytest tests/test_tq3_allreduce.py -v` — compression quality simulation
• `python tests/bench_tq3_allreduce.py` — break-even bandwidth analysis
• Multi-GPU integration test (2+ GPUs)

🤖 Generated with Claude Code

[influenist]

Closing — CUDA kernels were never compiled or tested on real hardware. Will revisit after the KV cache PR (#182) is reviewed.