[AMD] Add basics to allow bypass LDS for dot RHS#5350
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[AMD] Add basics to allow bypass LDS for dot RHS#5350antiagainst merged 16 commits intotriton-lang:mainfrom
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…#5350)" (triton-lang#5708) Reverting, as I have to revert [cec1db5](triton-lang@cec1db5), (which this change relies on) due to regression in internal tests.
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…#5350)" (triton-lang#5708) Reverting, as I have to revert [cec1db5](triton-lang@cec1db5), (which this change relies on) due to regression in internal tests.
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…ton-lang#5350)" (triton-lang#5708)" This reverts commit 216385e.
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…ton-lang#5350)" (triton-lang#5708)" This reverts commit 216385e.
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…ton-lang#5350)" (triton-lang#5708)" This reverts commit 216385e.
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This pull request supersedes #4856.
The AMDBypassLDSForDotOperandPass implements a strategy to bypass using the
Local Data Share (LDS) for one of the operands in an MFMA dot operation.
Under certain conditions, the dot layout of one of the operands allows direct
loading from HBM to VGPRs in the MFMA dot layout, without losing of vectorization of global loads
or increasing the number of global loads due to shared data between threads.
The required conditions are:
K-Major Tensor Layout:
The operand we want to bypass LDS for must be K-major (i.e., row-major for
operand 0 or column-major for operand 1). This supports vectorized global
load instructions, as MFMA instructions require each thread to hold B
operand elements along the K dimension.
kWidth * sizeof(dataType) == 128:
Using the maximum kWidth for a specific data type ensures optimal global
load vectorization (e.g., using global_load_dwordx4 instructions).
Single Warp per CTA Dimension:
Either warpsPerCTA[ndim] == 1 for operand A bypass or warpsPerCTA[mDim] ==
1 for operand B bypass. This guarantees that each tensor element is
handled by exactly one thread, maintaining the same number of global loads
as in the blocked layout (i.e., each element is loaded only once).