Skip to content

[BACKEND] Fix inline asm bug for multiple packed <32bit output #5273

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
ThomasRaoux merged 3 commits into from
Nov 27, 2024
Merged

[BACKEND] Fix inline asm bug for multiple packed <32bit output #5273

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
e4b1511
[BACKEND] Fix inline asm bug for multiple packed <32bit output
ggengnv Nov 27, 2024
5705e08
Check for output signature in test
ggengnv Nov 27, 2024
71d528b
Run pre-commit
ggengnv Nov 27, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 2 additions & 3 deletions lib/Conversion/TritonGPUToLLVM/ElementwiseOpToLLVM.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -325,13 +325,12 @@ struct ElementwiseInlineAsmOpConversion
// asmResults is a flat struct; pack its values into
// [return_value][op.getPackedElement()].
SmallVector<SmallVector<Value>> ret(op->getNumResults());
int structIdx = 0;
for (int i = 0; i < op->getNumResults(); i++) {
int structIdx = 0;
for (int j = 0; j < op.getPackedElement(); j++) {
Value val;
if (asmRetTypes.size() > 1) {
val =
extract_val(asmResults, i * op.getPackedElement() + structIdx++);
val = extract_val(asmResults, structIdx++);
} else {
val = asmResults;
}
Expand Down
13 changes: 13 additions & 0 deletions test/Conversion/tritongpu_to_llvm.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1897,3 +1897,16 @@ module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 :
tt.return
}
}

// -----

// CHECK: inline_asm_pack
#blocked = #triton_gpu.blocked<{sizePerThread = [16, 1], threadsPerWarp = [4, 8], warpsPerCTA = [1, 4], order = [0, 1]}>
module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 4 : i32, triton_gpu.target = "cuda:90", "triton_gpu.threads-per-warp" = 32 : i32} {
// check specifically for the case where asm has two results, pack > 1, and the result bitwidth is < 32
Copy link
Copy Markdown
Collaborator

@ThomasRaoux ThomasRaoux Nov 27, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

nit: could you add a simple check showing the signature of the op generated

Copy link
Copy Markdown
Contributor Author

@ggengnv ggengnv Nov 27, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

yep, just added check for signature with types

tt.func public @inline_asm_pack(%80: tensor<64x64xi8, #blocked>) attributes {noinline = false} {
// CHECK: llvm.inline_asm asm_dialect {{.*}} (vector<4xi8>) -> !llvm.struct<(vector<2xbf16>, vector<2xbf16>, vector<2xbf16>, vector<2xbf16>)>
%83:2 = tt.elementwise_inline_asm "" {constraints = "=r,=r,=r,=r,r", packed_element = 4 : i32, pure = true} %80 : tensor<64x64xi8, #blocked> -> tensor<64x64xbf16, #blocked>, tensor<64x64xbf16, #blocked>
tt.return
}
}