[backend][fp8] Float8E4M3FNUZ -> Float8E4M3FN for NVIDIA PTX

[chsigg]

Fix MLIR type used for e4m3 fp8 type in NVIDIA PTX codegen.

#3681

[ThomasRaoux]

LGTM

[yiakwy-xpu-ml-framework-team]

Hi @chsigg AMD uses Float8E4M3FNUZ (bias == 8) instead of Float8E4M3FN (bias == 7). Will it be a problem if we modifying codes directly over TritonIR ?

[chsigg]

Hi @chsigg AMD uses Float8E4M3FNUZ (bias == 8) instead of Float8E4M3FN (bias == 7). Will it be a problem if we modifying codes directly over TritonIR ?

@acollins3 tried to keep this generic in openxla#8 (comment) where it's not backend-specific yet. I hope we manage for both fp8 types to coexist. I'm not sure what you mean by 'modifying codes directly over TritonIR'.

[yiakwy-xpu-ml-framework-team]

Hi @chsigg AMD uses Float8E4M3FNUZ (bias == 8) instead of Float8E4M3FN (bias == 7). Will it be a problem if we modifying codes directly over TritonIR ?

@acollins3 tried to keep this generic in openxla#8 (comment) where it's not backend-specific yet. I hope we manage for both fp8 types to coexist. I'm not sure what you mean by 'modifying codes directly over overriding'.

Because I see we overiding existing fp8 without adding a new fp8 (I guess adding a new one) is more robust. Float8E4M3FN uses 0b1111 111 to represent NaNs, while Float8E4M3FNUZ uses 0b1000 000.

I am not sure this will be a problem. I share this information to relevant people to check against. Thank you for the fast response.