Update LLVM to 7ec6f1771114 #10503
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ThomasRaoux merged 6 commits intoJun 5, 2026
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ThomasRaoux
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zhanglx13
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June 5, 2026 19:35
- Dropped -Os and -Oz after llvm/llvm-project#191363 - Emit scalar `{add,sub,mul}.rn.bf16` ops after llvm/llvm-project#190414 - Also changed to avoid hardcoding line numbers in test_line_info.py - Add identifier/discriminator arguments to DICompositeTypeAttr::get calls after llvm/llvm-project#195321 - Pass MCRegisterInfo and MCSubtargetInfo by reference when constructing MCContext after llvm/llvm-project#195032 - Replace NVVM::Barrier0Op and nvvm.barrier0 test expectations with NVVM::BarrierOp/nvvm.barrier after llvm/llvm-project#195608
This reverts commit 8af25a8.
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FYI: The title of this pull request can be misleading--it actually bumps to llvm/llvm-project@62b7cf9623fc. |
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oops sorry |
This was referenced Jun 24, 2026
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Jul 5, 2026
* Dropped -Os and -Oz after llvm/llvm-project#191363 * Emit scalar {add,sub,mul}.rn.bf16 ops after llvm/llvm-project#190414 * Also changed to avoid hardcoding line numbers in test_line_info.py * Add identifier/discriminator arguments to DICompositeTypeAttr::get * calls after llvm/llvm-project#195321 * Pass MCRegisterInfo and MCSubtargetInfo by reference when constructing * MCContext after llvm/llvm-project#195032 * Replace NVVM::Barrier0Op and nvvm.barrier0 test expectations with * NVVM::BarrierOp/nvvm.barrier after llvm/llvm-project#195608 * Update AMD target parser includes after llvm/llvm-project#198433 * Add explicit TypeID for AMD UniformityAnalysis after llvm/llvm-project#199634 * Update finite-trip-count AMD range analysis after llvm/llvm-project#196616 * Update NVVM::BarrierOp creation after llvm/llvm-project#199404 also disable SLP vectorizer on sm_80 to workaround a ptxas bug --------- Co-authored-by: Lei Zhang <antiagainst@gmail.com> Co-authored-by: Lei Zhang <Lei.Zhang2@amd.com>
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nvvm.barrier0op llvm/llvm-project#195608also disable SLP vectorizer on sm_80 to workaround a ptxas bug