Verilator open-source SystemVerilog simulator and lint system

VeeR EL2 Core

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

A hardware rasterizer created for real-time rendering

Extended and external tests for Verilator testing

An abstraction library for interfacing EDA tools

The ZipCPU blog

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

An open source utility to build and simulate cores.

A small, light weight, RISC CPU soft core

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)

HDL support for VS Code

Digital Interpolation Techniques Applied to Digital Signal Processing

System Level Simulation and ASIC hardening flow for various designs using Systemverilog, Verilator and OpenROAD

Simple implementation of SOC around PicoRV32 soft core.

Compile and Install of Verilator Tool (Compiles synthesizable Verilog / SystemVerilog into C++ and SystemC code)

FPGA based GPU for rendering ray marched scenes.

Learn Verilog hardware design and verification using Verilator

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.