VeeR EH1 core
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Updated
May 29, 2023 - SystemVerilog
VeeR EH1 core
VeeR EL2 Core
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
Universal Verification Methodology (UVM) base libraries, with edits for Verilator
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
SystemVerilog implemention of QEMU PCI edu device
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
A single cycle processor implementing a subset of the ARMv7 ISA.
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
NESystem Verilog
Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.
Experimental RISCV implementation
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