Pick your favorite language to verify your chip.

xspcomm encapsulates the DPI-based digital circuit and provides various high-level language operation interfaces.

Simple Theorem Prover, an efficient SMT solver for bitvectors

MQT QCEC - A tool for Quantum Circuit Equivalence Checking

Automatic verification of LLVM optimizations

An advanced SAT solver

An open-source design automation framework for Field-coupled Nanotechnologies

System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .

[Mirror of https://gitlab.braingenix.org/carboncopies/] BrainGenix-EVM offers evaluation metrics for assessing accuracy in reconstructing neuronal systems, crucial for Whole Brain Emulation. Our platform provides both structural and functional validation metrics, ensuring fidelity in neural network topology and behavior replication.

A Modeling and Verification Platform for SoCs using ILAs

The Autograph protocol

Library for Data Decision Diagrams and Set Decision Diagrams

10GbE XGMII TCP/IPv4 packet generator for Verilog

Teaching and Learning Software Verification via SVF

Synchronous, single-threaded, library-only SYCL implementation for debugging and verification.

A library for building abstract interpretation-based analyses

A header-only C++ library for system-level verification and declarative testing of real-time systems with Python bindings.

Model checker for Maude systems controlled by strategies

Open-Source Framework for Development, Simulation and Benchmarking of Behavior Planning Algorithms for Autonomous Driving

Parallel Verification of Propositional Natural-Deduction Proof Graphs