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12 public repositories
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An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII,用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。
Updated
Sep 14, 2023
Verilog
Gigabit Ethernet UDP communication driver
Updated
Jul 26, 2019
Verilog
Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
Updated
Dec 31, 2022
Verilog
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
Updated
Jan 10, 2024
Verilog
ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor
Updated
Dec 13, 2021
Verilog
技術書展13(2022/9/10 ~ 9/25) にて頒布した『FPGAによるネットワーク機器完全自作実践』のサポートリポジトリです
Updated
Feb 1, 2023
Verilog
Example platform for Xilinx MII_to_RMII IP on Arty A7-35T, including ethernet RX and TX
Updated
Jun 30, 2020
Verilog
VC707 ETHERNET Xilinx Project
Updated
Apr 9, 2018
Verilog
Example platform for Xilinx AXI_EthernetLite (MII) on Arty A7-35T, including active TX driven by AXI Traffic Generator and dummy RX
Updated
Jun 29, 2020
Verilog
Transfers data from an ADC to a PC via ethernet
Updated
Jun 7, 2018
Verilog
Bloques y bancos de pruebas PCS para Ethernet 10G.
Updated
Aug 23, 2024
Verilog
About Bloques y bancos de pruebas MAC para Ethernet 10G.
Updated
Aug 10, 2024
Verilog
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