This project demonstrates DSP capabilities of Terasic DE2-115
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Updated
Jun 22, 2018 - Verilog
This project demonstrates DSP capabilities of Terasic DE2-115
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
Matrix multiplication on multiple Nios II cores
This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode)
Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)
This project is an implementation of the popular card game UNO on the DE2-115 FPGA board.
Дипломная работа специалиста за 2015 год на тему "Акустическая система мониторинга на основе пространственной фильтрации звуковых сигналов".
FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.
Development of an FPGA-based graphics controller
A platformer game based on Gravity Guy, using a DE2 hardware board
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