[PAC][CodeGen] Do not emit trivial 'mov xN, xN' on tail call (llvm#10…

…9100) Under some conditions, a trivial `mov xN xN` instruction was emitted on tail calls. Consider the following code: ``` class Test { public: virtual void f() {} }; void call_f(Test *t) { t->f(); } ``` Correponding assembly: ``` _Z6call_fP4Test: ldr x16, [x0] mov x17, x0 movk x17, llvm#6503, lsl llvm#48 autda x16, x17 ldr x1, [x16] =====> mov x16, x16 movk x16, llvm#54167, lsl llvm#48 braa x1, x16 ``` This patch makes such movs being omitted. Co-authored-by: Anatoly Trosinenko <[email protected]>
tmsri · Sep 19, 2024 · 8909e6d · 8909e6d
1 parent 87ce5c4
commit 8909e6d
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Showing 2 changed files with 27 additions and 5 deletions.
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -2510,11 +2510,12 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
     unsigned DiscReg = AddrDisc;
     if (Disc) {
       if (AddrDisc != AArch64::NoRegister) {
-        EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ORRXrs)
-                                         .addReg(ScratchReg)
-                                         .addReg(AArch64::XZR)
-                                         .addReg(AddrDisc)
-                                         .addImm(0));
+        if (ScratchReg != AddrDisc)
+          EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ORRXrs)
+                                           .addReg(ScratchReg)
+                                           .addReg(AArch64::XZR)
+                                           .addReg(AddrDisc)
+                                           .addImm(0));
         EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::MOVKXi)
                                          .addReg(ScratchReg)
                                          .addReg(ScratchReg)

diff --git a/llvm/test/CodeGen/AArch64/ptrauth-call.ll b/llvm/test/CodeGen/AArch64/ptrauth-call.ll
@@ -167,6 +167,27 @@ define i32 @test_tailcall_ib_var(ptr %arg0, ptr %arg1) #0 {
   ret i32 %tmp1
 }
 
+define void @test_tailcall_omit_mov_x16_x16(ptr %objptr) #0 {
+; CHECK-LABEL: test_tailcall_omit_mov_x16_x16:
+; CHECK:         ldr     x16, [x0]
+; CHECK:         mov     x17, x0
+; CHECK:         movk    x17, #6503, lsl #48
+; CHECK:         autda   x16, x17
+; CHECK:         ldr     x1, [x16]
+; CHECK:         movk    x16, #54167, lsl #48
+; CHECK:         braa    x1, x16
+  %vtable.signed = load ptr, ptr %objptr, align 8
+  %objptr.int = ptrtoint ptr %objptr to i64
+  %vtable.discr = tail call i64 @llvm.ptrauth.blend(i64 %objptr.int, i64 6503)
+  %vtable.signed.int = ptrtoint ptr %vtable.signed to i64
+  %vtable.unsigned.int = tail call i64 @llvm.ptrauth.auth(i64 %vtable.signed.int, i32 2, i64 %vtable.discr)
+  %vtable.unsigned = inttoptr i64 %vtable.unsigned.int to ptr
+  %virt.func.signed = load ptr, ptr %vtable.unsigned, align 8
+  %virt.func.discr = tail call i64 @llvm.ptrauth.blend(i64 %vtable.unsigned.int, i64 54167)
+  tail call void %virt.func.signed(ptr %objptr) [ "ptrauth"(i32 0, i64 %virt.func.discr) ]
+  ret void
+}
+
 define i32 @test_call_ia_arg(ptr %arg0, i64 %arg1) #0 {
 ; DARWIN-LABEL: test_call_ia_arg:
 ; DARWIN-NEXT:    stp x29, x30, [sp, #-16]!