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drivers: udc: mcux_ehci: rework control transfer handling#3

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tmon-nordic merged 1 commit intotmon-nordic:rework-udcfrom
MarkWangChinese:feature/rework-udc-mcux-ehci
Feb 27, 2026
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drivers: udc: mcux_ehci: rework control transfer handling#3
tmon-nordic merged 1 commit intotmon-nordic:rework-udcfrom
MarkWangChinese:feature/rework-udc-mcux-ehci

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allocate control buffers in stack

allocate control buffers in stack

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
@tmon-nordic tmon-nordic merged commit 8a5cd98 into tmon-nordic:rework-udc Feb 27, 2026
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tmon-nordic pushed a commit that referenced this pull request Mar 11, 2026
1. Mostly complete.  Supports MPU, userspace, PSPLIM-based stack
guards, and FPU/DSP features.  ARMv8-M secure mode "should" work but I
don't know how to test it.

2. Designed with an eye to uncompromising/best-in-industry cooperative
context switch performance.  No PendSV exception nor hardware
stacking/unstacking, just a traditional "musical chairs" switch.
Context gets saved on process stacks only instead of split between
there and the thread struct.  No branches in the core integer switch
code (and just one in the FPU bits that can't be avoided).

3. Minimal assembly use; arch_switch() itself is ALWAYS_INLINE, there
is an assembly stub for exception exit, and that's it beyond one/two
instruction inlines elsewhere.

4. Selectable at build time, interoperable with existing code.  Just
use the pre-existing CONFIG_USE_SWITCH=y flag to enable it.  Or turn
it off to evade regressions as this stabilizes.

5. Exception/interrupt returns in the common case need only a single C
function to be called at the tail, and then return naturally.
Effectively "all interrupts are direct now".  This isn't a benefit
currently because the existing stubs haven't been removed (see #4),
but in the long term we can look at exploiting this.  The boilerplate
previously required is now (mostly) empty.

6. No support for ARMv6 (Cortex M0 et. al.) thumb code.  The expanded
instruction encodings in ARMv7 are a big (big) win, so the older cores
really need a separate port to avoid impacting newer hardware.
Thankfully there isn't that much code to port (see #3), so this should
be doable.

Signed-off-by: Andy Ross <andyross@google.com>
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