Limitations of RegMon Monitoring

Register Reading Delay

The MAC state registers change with the clock speed of the Atheros WiFi card, and typically, with 40 MHz in 802.11a or 44 MHz at 802.11g 20MHz channels. As RegMon is one order of magnitude slower in terms of sampling these MAC state registers, we investigate the processing delays added by register readings to quantify the measurement error. Before the MAC state registers are read, a specific MIB (Management Information Base) register write operation is required in order to freeze the MAC-state register content until the read operation finished and the MIB is unlocked by a second write operation. This lock before read mechanism is necessary for all Atheros drivers: Madwifi, Ath5k and Ath9k. To quantify the duration of RegMon MAC-state register reading, we measure the execution duration by comparing the TSF timestamp before and after the actual register reading takes place. A full cycle, which includes freezing all MAC-state registers, reading each of the four registers and unfreezing them, takes approximately 7 μs in all of our measurements and, across all drivers and also with both Asus and RSpro hardware. As TSF is measured with an accuracy of 1 μs, the absolute error of a full read cycle of all four MAC-state registers is 7 ± 1 μs. The impact of this error depends on the sampling interval used, e.g., if MAC-state registers are sampled at 20kHz, which corresponds to a sampling interval of 50 μs, this translates to a relative error of 16%. However, most of our power control experiments need a RegMon sampling speed of at most 1000Hz, which introduces a relative error of about 0.9 %.