Merge pull request #488 from mmaka1/ssp-init

dai: ssp: dynamic device descriptor initialization
thesofproject · Oct 19, 2018 · 6baff99 · 6baff99
2 parents 459ccd2 + 550180a
commit 6baff99
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Showing 7 changed files with 32 additions and 145 deletions.
diff --git a/src/platform/apollolake/include/platform/interrupt.h b/src/platform/apollolake/include/platform/interrupt.h
@@ -124,18 +124,10 @@
 	SOF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA0(channel), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
 #define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \
 	SOF_IRQ(IRQ_BIT_LVL5_LP_GP_DMA1(channel), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP0_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP1_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(1), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP2_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(2), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP3_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(3), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP4_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(4), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP5_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(5), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
+#define IRQ_EXT_SSPx_LVL5(x, xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL5_SSP(x), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
 #define IRQ_EXT_DMIC_LVL5(xcpu) \
 	SOF_IRQ(IRQ_BIT_LVL5_DMIC, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
 

diff --git a/src/platform/apollolake/include/platform/memory.h b/src/platform/apollolake/include/platform/memory.h
@@ -261,7 +261,7 @@
 
 /* bss data */
 #define SOF_BSS_DATA_START	(SOF_TEXT_BASE + SOF_TEXT_SIZE + SOF_DATA_SIZE)
-#define SOF_BSS_DATA_SIZE	0x8700
+#define SOF_BSS_DATA_SIZE	0x9000
 
 /* Stack configuration */
 #define SOF_STACK_SIZE		0x1000

diff --git a/src/platform/cannonlake/include/platform/interrupt.h b/src/platform/cannonlake/include/platform/interrupt.h
@@ -125,14 +125,10 @@
 	SOF_ID_IRQ(0, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
 #define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \
 	SOF_ID_IRQ(1, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP0_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP1_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(1), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP2_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(2), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP3_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(3), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
+#define IRQ_EXT_SSPx_LVL5(x, xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL5_SSP(x), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
 #define IRQ_EXT_DMIC_LVL5(xcpu) \
 	SOF_IRQ(IRQ_BIT_LVL5_DMIC, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
 

diff --git a/src/platform/cannonlake/include/platform/memory.h b/src/platform/cannonlake/include/platform/memory.h
@@ -231,7 +231,7 @@
 /* text and data share the same HP L2 SRAM on Cannonlake */
 #define SOF_TEXT_START		0xBE040400
 #define SOF_TEXT_BASE		(SOF_TEXT_START)
-#define SOF_TEXT_SIZE		(0x1a000 - 0x400)
+#define SOF_TEXT_SIZE		(0x1b000 - 0x400)
 
 /* initialized data */
 #define SOF_DATA_START		(SOF_TEXT_BASE + SOF_TEXT_SIZE)

diff --git a/src/platform/icelake/include/platform/interrupt.h b/src/platform/icelake/include/platform/interrupt.h
@@ -125,14 +125,10 @@
 	SOF_ID_IRQ(0, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
 #define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \
 	SOF_ID_IRQ(1, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP0_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP1_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(1), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP2_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(2), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP3_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(3), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
+#define IRQ_EXT_SSPx_LVL5(x, xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL5_SSP(x), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
 #define IRQ_EXT_DMIC_LVL5(xcpu) \
 	SOF_IRQ(IRQ_BIT_LVL5_DMIC, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
 

diff --git a/src/platform/intel/cavs/dai.c b/src/platform/intel/cavs/dai.c
@@ -47,112 +47,7 @@
 #include <string.h>
 #include <config.h>
 
-static struct dai ssp[] = {
-{
-	.type = SOF_DAI_INTEL_SSP,
-	.index = 0,
-	.plat_data = {
-		.base		= SSP_BASE(0),
-		.irq		= IRQ_EXT_SSP0_LVL5(0),
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= SSP_BASE(0) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP0_TX,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= SSP_BASE(0) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP0_RX,
-		}
-	},
-	.ops		= &ssp_ops,
-},
-{
-	.type = SOF_DAI_INTEL_SSP,
-	.index = 1,
-	.plat_data = {
-		.base		= SSP_BASE(1),
-		.irq		= IRQ_EXT_SSP1_LVL5(0),
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= SSP_BASE(1) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP1_TX,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= SSP_BASE(1) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP1_RX,
-		}
-	},
-	.ops		= &ssp_ops,
-},
-{
-	.type = SOF_DAI_INTEL_SSP,
-	.index = 2,
-	.plat_data = {
-		.base		= SSP_BASE(2),
-		.irq		= IRQ_EXT_SSP2_LVL5(0),
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= SSP_BASE(2) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP2_TX,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= SSP_BASE(2) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP2_RX,
-		}
-	},
-	.ops		= &ssp_ops,
-},
-#if defined(CONFIG_APOLLOLAKE)
-{
-	.type = SOF_DAI_INTEL_SSP,
-	.index = 3,
-	.plat_data = {
-		.base		= SSP_BASE(3),
-		.irq		= IRQ_EXT_SSP3_LVL5(0),
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset		= SSP_BASE(3) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP3_TX,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset		= SSP_BASE(3) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP3_RX,
-		}
-	},
-	.ops		= &ssp_ops,
-},
-{
-	.type = SOF_DAI_INTEL_SSP,
-	.index = 4,
-	.plat_data = {
-		.base		= SSP_BASE(4),
-		.irq		= IRQ_EXT_SSP4_LVL5(0),
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset 	= SSP_BASE(4) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP4_TX,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset 	= SSP_BASE(4) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP4_RX,
-		}
-	},
-	.ops		= &ssp_ops,
-},
-{
-	.type = SOF_DAI_INTEL_SSP,
-	.index = 5,
-	.plat_data = {
-		.base		= SSP_BASE(5),
-		.irq		= IRQ_EXT_SSP5_LVL5(0),
-		.fifo[SOF_IPC_STREAM_PLAYBACK] = {
-			.offset 	= SSP_BASE(5) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP5_TX,
-		},
-		.fifo[SOF_IPC_STREAM_CAPTURE] = {
-			.offset 	= SSP_BASE(5) + SSDR,
-			.handshake	= DMA_HANDSHAKE_SSP5_RX,
-		}
-	},
-	.ops		= &ssp_ops,
-},
-#endif
-};
+static struct dai ssp[(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT)];
 
 #if defined CONFIG_DMIC
 
@@ -230,8 +125,20 @@ int dai_init(void)
 	int i;
 
 	/* init ssp */
-	/* TODO: move all the properties initialization here */
 	for (i = 0; i < ARRAY_SIZE(ssp); i++) {
+		ssp[i].type = SOF_DAI_INTEL_SSP;
+		ssp[i].index = i;
+		ssp[i].ops = &ssp_ops;
+		ssp[i].plat_data.base = SSP_BASE(i);
+		ssp[i].plat_data.irq = IRQ_EXT_SSPx_LVL5(i, 0);
+		ssp[i].plat_data.fifo[SOF_IPC_STREAM_PLAYBACK].offset =
+			SSP_BASE(i) + SSDR;
+		ssp[i].plat_data.fifo[SOF_IPC_STREAM_PLAYBACK].handshake =
+			DMA_HANDSHAKE_SSP0_TX + 2 * i;
+		ssp[i].plat_data.fifo[SOF_IPC_STREAM_CAPTURE].offset =
+			SSP_BASE(i) + SSDR;
+		ssp[i].plat_data.fifo[SOF_IPC_STREAM_CAPTURE].handshake =
+			DMA_HANDSHAKE_SSP0_RX + 2 * i;
 		/* initialize spin locks early to enable ref counting */
 		spinlock_init(&ssp[i].lock);
 	}

diff --git a/src/platform/suecreek/include/platform/interrupt.h b/src/platform/suecreek/include/platform/interrupt.h
@@ -127,14 +127,10 @@
 	SOF_ID_IRQ(0, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
 #define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \
 	SOF_ID_IRQ(1, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP0_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP1_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(1), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP2_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(2), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
-#define IRQ_EXT_SSP3_LVL5(xcpu) \
-	SOF_IRQ(IRQ_BIT_LVL5_SSP(3), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
+#define IRQ_EXT_SSPx_LVL5(x, xcpu) \
+	SOF_IRQ(IRQ_BIT_LVL5_SSP(x), 5, xcpu, IRQ_NUM_EXT_LEVEL5)
+
 #define IRQ_EXT_DMIC_LVL5(xcpu) \
 	SOF_IRQ(IRQ_BIT_LVL5_DMIC, 5, xcpu, IRQ_NUM_EXT_LEVEL5)