[WIP] [TMS7000] Tune bus cycles

tgtakaoka · Jun 18, 2024 · 7313be8 · 7313be8
1 parent ba2d52d
commit 7313be8
Showing 1 changed file with 53 additions and 26 deletions.
diff --git a/debugger/tms7000/pins_tms7000.cpp b/debugger/tms7000/pins_tms7000.cpp
@@ -40,14 +40,28 @@ struct PinsTms7000 Pins;
 // clang-format on
 
 namespace {
-
-constexpr auto clkin_hi_ns = 500;
-constexpr auto clkin_lo_ns = 500;
-constexpr auto clk2_hi_ns = 500;
-constexpr auto clk2_lo_ns = 500;
-constexpr auto clk4_hi_ns = 250;
-constexpr auto clk4_lo_ns = 250;
-constexpr auto clk4_hi_serial = 200;
+// /2: CLKIN=5MHz
+constexpr auto clkin_hi_ns = 200;     // 100 ns
+constexpr auto clkin_lo_ns = 200;     // 100 ns
+constexpr auto clk2_hi_ns = 200;      // 100 ns
+constexpr auto clk2_lo_ns = 200;      // 100 ns
+constexpr auto clk_hi_ns = 200;       // 100 ns
+constexpr auto clk_lo_ns = 200;       // 100 ns
+constexpr auto clk_lo_addr = 200;     // 100 ns
+constexpr auto clk_hi_dir = 200;      // 100 ns
+constexpr auto clk_lo_mread = 200;    // 100 ns
+constexpr auto clk_lo_inject = 200;   // 100 ns
+constexpr auto clk_hi_output = 200;   // 100 ns
+constexpr auto clk_hi_input = 200;    // 100 ns
+constexpr auto clk_lo_nread = 200;    // 100 ns
+constexpr auto clk_lo_write = 200;    // 100 ns
+constexpr auto clk_hi_get = 200;      // 100 ns
+constexpr auto clk_lo_mwrite = 200;   // 100 ns
+constexpr auto clk_lo_capture = 200;  // 100 ns
+constexpr auto clk_lo_get = 200;      // 100 ns
+constexpr auto clk4_hi_ns = 100;      //  50 ns
+constexpr auto clk4_lo_ns = 100;      //  50 ns
+constexpr auto clk4_hi_serial = 80;   //  50 ns
 
 inline void clkin_hi() {
     digitalWriteFast(PIN_CLKIN, HIGH);
@@ -250,59 +264,72 @@ Signals *PinsTms7000::prepareCycle() const {
         clk_cycle();
     // CLKOUT=H, ALATCH=H
     clk_hi();
-    delayNanoseconds(clk2_hi_ns);
+    delayNanoseconds(clk_hi_ns);
     // CLKOUT=L
     clk_lo();
+    assert_debug();
     s->getAddress();
-    delayNanoseconds(clk2_lo_ns);
+    negate_debug();
+    delayNanoseconds(clk_lo_addr);
     // CLKOUT=H
     clk_hi();
-    delayNanoseconds(clk2_hi_ns);
+    delayNanoseconds(clk_hi_dir);
+    assert_debug();
     s->getDirection();
+    negate_debug();
     return s;
 }
 
 Signals *PinsTms7000::completeCycle(Signals *s) const {
+    clk_lo();
     if (s->read()) {  // External read
-        clk_lo();
         if (s->readMemory()) {
             s->data = Memory.read(s->addr);
+            assert_debug();
+            s->outData();
+            negate_debug();
+            delayNanoseconds(clk_lo_mread);
         } else {
-            ;  // inject
+            assert_debug();
+            s->outData();
+            negate_debug();
+            delayNanoseconds(clk_lo_inject);
         }
-        delayNanoseconds(clk2_lo_ns);
         // CLKOUT=L
         clk_hi();
-        s->outData();
-        delayNanoseconds(clk2_hi_ns);
+        delayNanoseconds(clk_hi_ns);
         clk_lo();
-        delayNanoseconds(clk2_lo_ns);
+        delayNanoseconds(clk_lo_ns);
         // CLKOUT=H
         clk_hi();
         while (signal_enable() == LOW)
             ;
+        assert_debug();
         s->inputMode();
-        delayNanoseconds(clk2_hi_ns);
+        negate_debug();
+        delayNanoseconds(clk_hi_input);
         clk_lo();
-        delayNanoseconds(clk2_lo_ns);
+        delayNanoseconds(clk_lo_nread);
     } else if (s->write()) {  // External write
-        clk_lo();
-        delayNanoseconds(clk2_lo_ns);
+        delayNanoseconds(clk_lo_write);
         // CLKOUT=L
         clk_hi();
+        assert_debug();
         s->getData();
-        delayNanoseconds(clk2_hi_ns);
+        negate_debug();
+        delayNanoseconds(clk_hi_get);
         clk_lo();
         if (s->writeMemory()) {
             Memory.write(s->addr, s->data);
+            delayNanoseconds(clk_lo_mwrite);
         } else {
-            ;  // capture
+            delayNanoseconds(clk_lo_capture);
         }
-        delayNanoseconds(clk2_lo_ns);
     } else {  // Internal cycle
-        clk_lo();
-        delayNanoseconds(clk2_lo_ns);
+        delayNanoseconds(clk_lo_get);
+        assert_debug();
         s->getData();
+        negate_debug();
     }
     Signals::nextCycle();
     while (signal_alatch() == LOW)