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@tgtakaoka
tgtakaoka committed Jun 13, 2024
1 parent 1febd88 commit 38d3bb8
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Showing 2 changed files with 84 additions and 80 deletions.
153 changes: 78 additions & 75 deletions debugger/tms7000/pins_tms7000.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,27 +41,26 @@ struct PinsTms7000 Pins;

namespace {
// /2: CLKIN=5MHz
constexpr auto clkin_hi_ns = 200; // 100 ns
constexpr auto clkin_lo_ns = 200; // 100 ns
constexpr auto clk2_hi_ns = 200; // 100 ns
constexpr auto clk2_lo_ns = 200; // 100 ns
constexpr auto clk_hi_ns = 200; // 100 ns
constexpr auto clk_lo_ns = 200; // 100 ns
constexpr auto clk_lo_addr = 200; // 100 ns
constexpr auto clk_hi_dir = 200; // 100 ns
constexpr auto clk_lo_mread = 200; // 100 ns
constexpr auto clk_lo_inject = 200; // 100 ns
constexpr auto clk_hi_output = 200; // 100 ns
constexpr auto clk_hi_input = 200; // 100 ns
constexpr auto clk_lo_nread = 200; // 100 ns
constexpr auto clk_lo_write = 200; // 100 ns
constexpr auto clk_hi_get = 200; // 100 ns
constexpr auto clk_lo_mwrite = 200; // 100 ns
constexpr auto clk_lo_capture = 200; // 100 ns
constexpr auto clk_lo_get = 200; // 100 ns
constexpr auto clk4_hi_ns = 100; // 50 ns
constexpr auto clk4_lo_ns = 100; // 50 ns
constexpr auto clk4_hi_serial = 80; // 50 ns
constexpr auto clkin_hi_ns = 100; // 100 ns
constexpr auto clkin_lo_ns = 100; // 100 ns
constexpr auto clk2_hi_ns = 100; // 100 ns
constexpr auto clk2_lo_ns = 100; // 100 ns
constexpr auto clk_hi_ns = 45; // 100 ns
constexpr auto clk_lo_ns = 50; // 100 ns
constexpr auto clk_lo_inject = 46; // 100 ns
constexpr auto clk_lo_write = 40; // 100 ns
constexpr auto clk_hi_next = 0; // 100 ns
constexpr auto clk_lo_dir = 20; // 100 ns
constexpr auto clk_hi_output = 20; // 100 ns
constexpr auto clk_lo_get = 0; // 100 ns
constexpr auto clk_hi_get = 20; // 100 ns
constexpr auto clk_lo_capture = 50; // 100 ns
constexpr auto clk_lo_input = 0; // 100 ns
constexpr auto clk_lo_alatch = 60; // 100 ns
constexpr auto clk4_hi_ns = 35; // 50 ns
constexpr auto clk4_lo_ns = 35; // 50 ns
constexpr auto clk4_lo_serial = 15; // 50 ns
constexpr auto clk_lo_exec = 30; // 100 ns

inline void clkin_hi() {
digitalWriteFast(PIN_CLKIN, HIGH);
Expand Down Expand Up @@ -155,7 +154,7 @@ void clk2_lo() {

void clk4_hi() {
clkin_lo();
delayNanoseconds(clk4_hi_serial);
delayNanoseconds(clk4_lo_serial);
SerialH.loop();
clkin_hi();
}
Expand Down Expand Up @@ -224,6 +223,9 @@ void PinsTms7000::reset() {
negate_reset();
clk_cycle();
Signals::resetCycles();
// Wait for the first bus cycle
while (signal_alatch() == LOW)
clk_cycle();
// Clear IOCNT0 (>0100) to disable interrupts
cycle();
// Inject dummy reset vector >8000
Expand Down Expand Up @@ -259,81 +261,79 @@ void PinsTms7000::checkHardwareType() {
}

Signals *PinsTms7000::prepareCycle() const {
// ALATCH=H
auto s = Signals::put();
while (signal_alatch() == LOW)
clk_cycle();
// CLKOUT=H, ALATCH=H
clk_hi();
delayNanoseconds(clk_hi_ns);
// CLKOUT=L
clk_lo();
assert_debug();
s->getAddress();
negate_debug();
delayNanoseconds(clk_lo_addr);
// CLKOUT=H
clk_hi();
delayNanoseconds(clk_hi_dir);
assert_debug();
s->getDirection();
s->getAddress();
negate_debug();
return s;
}

Signals *PinsTms7000::completeCycle(Signals *s) const {
// ALATCH=L
clk_lo();
if (s->read()) { // External read
if (s->read()) {
if (s->readMemory()) {
s->data = Memory.read(s->addr);
assert_debug();
s->outData();
negate_debug();
delayNanoseconds(clk_lo_mread);
} else {
delayNanoseconds(clk_lo_inject);
}
} else {
delayNanoseconds(clk_lo_write);
}
// CLKOUT=H, ENABLE=L
clk_hi();
Signals::nextCycle();
delayNanoseconds(clk_hi_next);
// DATA=write data
clk_lo();
delayNanoseconds(clk_lo_dir);
assert_debug();
s->getDirection();
negate_debug();
if (s->external()) {
if (s->read()) {
// DATA=read data
clk_hi();
assert_debug();
s->outData();
negate_debug();
delayNanoseconds(clk_lo_inject);
delayNanoseconds(clk_hi_output);
clk_lo();
delayNanoseconds(clk_lo_ns);
} else {
delayNanoseconds(clk_lo_get);
// CLKOUT=L
clk_hi();
delayNanoseconds(clk_hi_get);
s->getData();
clk_lo();
if (s->writeMemory()) {
Memory.write(s->addr, s->data);
} else {
delayNanoseconds(clk_lo_capture);
}
}
// CLKOUT=L
// CLKOUT=L, ENABLE=H
clk_hi();
delayNanoseconds(clk_hi_ns);
// ALE=H
clk_lo();
delayNanoseconds(clk_lo_ns);
// CLKOUT=H
clk_hi();
while (signal_enable() == LOW)
;
delayNanoseconds(clk_lo_input);
assert_debug();
s->inputMode();
negate_debug();
delayNanoseconds(clk_hi_input);
clk_lo();
delayNanoseconds(clk_lo_nread);
} else if (s->write()) { // External write
delayNanoseconds(clk_lo_write);
// CLKOUT=L
clk_hi();
assert_debug();
s->getData();
negate_debug();
delayNanoseconds(clk_hi_get);
clk_lo();
if (s->writeMemory()) {
Memory.write(s->addr, s->data);
delayNanoseconds(clk_lo_mwrite);
} else {
delayNanoseconds(clk_lo_capture);
}
delayNanoseconds(clk_lo_alatch);
} else { // Internal cycle
delayNanoseconds(clk_lo_get);
assert_debug();
s->getData();
negate_debug();
}
Signals::nextCycle();
while (signal_alatch() == LOW)
clk_cycle();
// ALATCH=H
return s;
}

Expand Down Expand Up @@ -366,15 +366,18 @@ void PinsTms7000::execute(const uint8_t *inst, uint8_t len, uint8_t *buf,
s->inject(inst[inj]);
if (cap < max)
s->capture();
delayNanoseconds(clk_lo_exec);
completeCycle(s);
if (s->read()) {
if (inj == 0 && addr)
*addr = s->addr;
if (inj < len)
++inj;
} else if (s->write()) {
if (cap < max && buf)
buf[cap++] = s->data;
if (s->external()) {
if (s->read()) {
if (inj == 0 && addr)
*addr = s->addr;
if (inj < len)
++inj;
} else {
if (cap < max && buf)
buf[cap++] = s->data;
}
}
}
}
Expand Down
11 changes: 6 additions & 5 deletions debugger/tms7000/signals_tms7000.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,23 +9,24 @@ namespace tms7000 {

void Signals::getAddress() {
addr = busRead(ADDR);
cntl() = busRead(CNTL);
markFetch(false);
}

void Signals::getDirection() {
cntl() = busRead(CNTL);
markFetch(false);
}

bool Signals::external() const {
return (cntl() & CNTL_ENABLE) == 0;
}

bool Signals::read() const {
return (cntl() & (CNTL_ENABLE | CNTL_RW)) == CNTL_RW;
return (cntl() & CNTL_RW) == CNTL_RW;
}

bool Signals::write() const {
return (cntl() & (CNTL_ENABLE | CNTL_RW)) == 0;
return (cntl() & CNTL_RW) == 0;
}

bool Signals::intack() const {
Expand Down Expand Up @@ -53,9 +54,9 @@ void Signals::print() const {
if (fetch()) {
buffer[0] = 'F';
} else if (external()) {
buffer[0] = write() ? 'W' : 'R';
buffer[0] = read() ? 'R' : 'W';
} else {
buffer[0] = intack() ? 'I' : (cntl() & CNTL_RW) ? 'r' : 'w';
buffer[0] = intack() ? 'I' : (read() ? 'r' : 'w');
}
buffer.hex16(4, addr);
buffer.hex8(11, data);
Expand Down

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