Add basic conversion between ttir and linalg

tenstorrent · Dec 16, 2024 · 84f34dd · 84f34dd
1 parent 2a03931
commit 84f34dd
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/test/ttmlir/Conversion/TTIRToLinalg/ttir.mlir b/test/ttmlir/Conversion/TTIRToLinalg/ttir.mlir
@@ -8,8 +8,7 @@ module attributes{} {
     %arg2: tensor<32x32xf32>   // Output tensor (result stored here)
   ) -> tensor<32x32xf32> {
     %1 = "ttir.add"(%arg0, %arg1, %arg2) <{operandSegmentSizes = array<i32: 2, 1>, operand_constraints = [#any_device, #any_device, #any_device]}> : (tensor<32x32xf32>, tensor<32x32xf32>, tensor<32x32xf32>) -> tensor<32x32xf32>
-     // CHECK: [[VAL1:%[0-9]+]] = "linalg.add"(%arg{{[0-9]+}}, %arg{{[0-9]+}}, %arg{{[0-9]+}}){{.+}}: ([[TENSOR_SIZE]], [[TENSOR_SIZE]], [[TENSOR_SIZE]]) -> [[TENSOR_SIZE]]
-    //    %1 = linalg.add ins(%arg0, %arg1 : tensor<32x32xf32>, tensor<32x32xf32>) outs(%arg2 : tensor<32x32xf32>) -> tensor<32x32xf32>
+     // CHECK: [[VAL1:%[0-9]+]] = linalg.add ins(%arg{{[0-9]+}}, %arg{{[0-9]+}} : tensor<32x32xf32>, tensor<32x32xf32>) outs(%arg{{[0-9]+}} : tensor<32x32xf32>) -> tensor<32x32xf32>
     return %1 : tensor<32x32xf32>
   }
 }