Tilize with val padding results in L1 cache OOM

[nardoTT]

Ticket

Link to Github Issue #15950

Problem description

In the current implementation of multi-core tilize with val padding, the parallelization is only over the columns, meaning the whole row is being passed to the same core. This causes L1 OOM when the tensor has a large width

What's changed

In multi-core tilize, we are calculating the maximum available L1 and the estimated cb size. We are running the single core implementation if there isn't enough space. The multi-core implementation will be improved in the future to cover row and column parallelization

Checklist

• Post commit CI passes https://github.com/tenstorrent/tt-metal/actions/runs/12698362359
• Blackhole Post commit (if applicable)
• Model regression CI testing passes (if applicable)
• Device performance regression CI testing passes (if applicable)
• (For models and ops writers) Full new models tests passes
• New/Existing tests provide coverage for changes