Christoph Maier
Email address: [email protected]
21 March 2024
| Parameter | min | typ | max | unit | Notes |
|---|---|---|---|---|---|
| Operating Voltage | 3 | 3.3 | 5.5 | V | |
| Operating Temperature | -40 | 25 | 85 | °C | |
| Output current range | 0.2 | 1 | µA | ||
| Power consumption (enabled) | 10 | 20 | µA | Measured at 3.3V and 25 °C | |
| Power consumption (disabled) | 10 | 20 | nA | ||
| Output current accuracy | -2 | 0 | 2 | % | |
| Temperature coefficient | 50 | 100 | 200 | ppm/°C | |
| PSRR | 50 | 60 | 70 | dB | at 1 kHz |
| Output noise | 0.1 | 0.5 | 1 | nA/&sqrt;Hz | 0.1 … 10 Hz |
| Start-up time | 10 | 20 | 40 | µs | |
| Output impedance | 0.5 | 1 | 2 | kΩ | |
| Matching between sources | -1 | 0 | 1 | % | between branches |
Note: Specific current outputs are indicated below.
Output bias layout should be modular so that the output array can be extended/contracted as needed.
Outputs will be sourced from the power supply.
Receiving circuits will sink the current to ground.
The bias current distributor is a building block that really only makes sense
if it distributes bias currents (and voltages, as it were)
from other people's building blocks to other people's building blocks.
Practically any IC design comprises current paths between two or several power supplies.
In CMOS without noticeable gate current leakage, the quiescent current is essentially zero.
Analog designs are categorically different
in the sense that they generally have a set of branches
between power supply rails with specified voltages.
While digital standard cell design is very closely modeled
to the business model of Chokepoint Capitalism,
wherein every performer is reduced to the role of an interchangeable moron83,
analog design is, in principle, a free-for-all.
However, if you want to build a system on a chip
comprising the contributions of several skilled individuals,
these individuals need to agree on certain conventions common to each of their contributions.
- supply voltages
- branch currents
- bias voltages to generate the branch currents
This here building block is all about distributing finite, non-zero, branch currents,
the magnitude and polarity of which should ideally have been agreed among on in advance
by the individual contributors.
Significantly, such specifications are not part of the acceptability criteria enforced by efabless through unrealistically tight deadlines.
Since, however, the bias current distribution block makes no sense whatsoever
and cannot even be begun to design in earnest, here goes:
| Building block | Designer[s] | Ibranch | unit | Notes |
|---|---|---|---|---|
| sky130sbcs | Dr Luís Henrique Rodovalho Moreira de Lima | 280±20 | nA | available on silicon |
| sky130_rodovalho_ip__lpopamp | Dr Luís Henrique Rodovalho Moreira de Lima | 10 | μA | |
| sky130_ajc_ip__brownout | Robin Matthew Tsang | 200 | nA | |
| sky130_ajc_ip__overvoltage | Robin Matthew Tsang | 200 | nA | |
| sky130_vbl_ip__overvoltage | Lucas Daudt Franck, William Carrara Orlato | ??? | ??? | |
| sky130_td_ip__opamp_hp | Thomas Dexter | 40 | μA | scaled up from 100 nA Ibias input |
| sky130_ak_ip__cmos_vref | Adan Kvitschal | μA | from internal bias circuit | |
| sky130_ef_ip__bgrref_por | Stephen Wu | 32 | nA | derived from Vbg |
| sky130_od_ip__tempsensor | Or Dicker | 1.3 | nA | from internal bias circuit |
| Pin name | Use | Value |
|---|---|---|
| avdd | analog power | 3.3…5.5V |
| dvdd | digital power | 1.8V typ. |
| avss | analog ground | 0V |
| dvss | digital ground | 0V |
| ena[15:0] | current branch enable | [dvss…dvdd] |
| vbg | bandgap voltage | ??? |
| iref[15:0] | reference output current | Variable 50, 100, 200, 400, 600nA ??? |
| poweron | digital, master power on | [dvss…dvdd] |
Note any changes from the specification, such as if trim bits have been added.