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chisel3 MChache changes (mix of SInt and UInt)
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schoeberl committed Aug 8, 2019
1 parent 40f5b0d commit 759f455
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions hardware/src/main/scala/icache/MCache.scala
Original file line number Diff line number Diff line change
Expand Up @@ -208,7 +208,7 @@ class MCacheReplFifo() extends Module {
hitReg := Bool(true) //start fetch, we have again a hit!
wrPosReg := posReg
//update free space
freeSpaceReg := freeSpaceReg - io.ctrlrepl.wData(MCACHE_SIZE_WIDTH,0) + sizeVec(nextIndexReg)
freeSpaceReg := freeSpaceReg - io.ctrlrepl.wData(MCACHE_SIZE_WIDTH,0).toSInt + sizeVec(nextIndexReg).toSInt
//update tag fields
posVec(nextIndexReg) := nextPosReg
sizeVec(nextIndexReg) := io.ctrlrepl.wData(MCACHE_SIZE_WIDTH, 0)
Expand All @@ -224,7 +224,7 @@ class MCacheReplFifo() extends Module {
}
//free new space if still needed -> invalidate next method
when (freeSpaceReg < SInt(0)) {
freeSpaceReg := freeSpaceReg + sizeVec(nextTagReg)
freeSpaceReg := freeSpaceReg + sizeVec(nextTagReg).toSInt
sizeVec(nextTagReg) := UInt(0)
validVec(nextTagReg) := Bool(false)
nextTagReg := Mux(nextTagReg === UInt(METHOD_COUNT - 1), UInt(0), nextTagReg + UInt(1))
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