AArch64: align pair-wise spills on WoS to 16-byte (#166902)#11801
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compnerd merged 1 commit intoswiftlang:stable/21.xfrom Nov 12, 2025
Merged
AArch64: align pair-wise spills on WoS to 16-byte (#166902)#11801compnerd merged 1 commit intoswiftlang:stable/21.xfrom
compnerd merged 1 commit intoswiftlang:stable/21.xfrom
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Adjust the frame setup code for Windows ARM64 to attempt to align pair-wise spills to 16-byte boundaries. This enables us to properly emit the spills for custom clang calling convensions such as preserve most which spills r9-r15 which are normally nonvolatile registers. Even when using the ARM64EC opcodes for the unwinding, we cannot represent the spill if it is unaligned. (cherry picked from commit 2d8563f)
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@swift-ci please test |
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Adjust the frame setup code for Windows ARM64 to attempt to align pair-wise spills to 16-byte boundaries. This enables us to properly emit the spills for custom clang calling convensions such as preserve most which spills r9-r15 which are normally nonvolatile registers. Even when using the ARM64EC opcodes for the unwinding, we cannot represent the spill if it is unaligned.
(cherry picked from commit 2d8563f)