v1.9.7

What's Changed

• [rtl] add generic cache module (not used yet) by @stnolting in #842
• rtl cleanups and optimizations by @stnolting in #843
• ⚠️ remove Wishbone tag signal by @stnolting in #845
• ⚠️⚠️ Rename external bus interface by @stnolting in #846
• ✨ Add optional external bus interface cache (XCACHE) by @stnolting in #849
• ⚠️ processor configuration edits / clean-ups by @stnolting in #850
• Minor cache updates by @stnolting in #851
• [litex] update core complex wrapper by @stnolting in #852
• rework cache system by @stnolting in #853
• Connected SPI bus to on-board Flash and SPI peripheral by @lovelesh-mis in #854
• Update CFU example: use XTEA as "real world" demo application by @stnolting in #855
• Updated Performance test by @mikaelsky in #844

New Contributors

• @lovelesh-mis made their first contribution in #854

Full Changelog: v1.9.6...v1.9.7