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⚠️ Major code edits / cleanups #664
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Not really official...
for PMP regions 16..63
and control bus signal renaming
-> renamed to 'neorv32_cpu_lsu.vhd' ("load/store unit")
make sure bus access error trigger only kicks in during a valid bus access
- add external CSR interface - remove FPU CSRs (moved to FPU module) - remove PMP CSRs (moved to PMP module) - control bus signal re-namings
Hi @stnolting since you are already changing and updating stuff.. some small error just detected: in I could open a pr but I think that is overkill. How would you like such rather small errors to be fixed? Shall I collect them in a special draft pr where I could collect multiple smaller correction commits? Or am I allowed to directly push such small fixes to main? 🤔 |
Thanks for finding!
Sounds good to me.
I think you cannot push to |
neorv32_cpu_bus.vhd -> neorv32_cpu_lsu.vhd
("load/store unit")neorv32_cpu_pmp.vhd
[m]hpmcounter3[h]
to[m]hpmcounter15[h]
)ℹ️ Moving the entire PMP/FPU CSR logic into optional (
if ... generate
) design units ensures that all of the logic is trimmed when the according module is not enabled.