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[rtl] rlt/code cleanups & optimizations #442

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Nov 18, 2022
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[rtl] rlt/code cleanups & optimizations #442

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9b89cb9
[rtl] rlt/code cleanups & optimizations
stnolting Nov 14, 2022
edc433e
[CHANGELOG] add v1.7.7.9
stnolting Nov 14, 2022
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -32,6 +32,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12

| Date (*dd.mm.yyyy*) | Version | Comment |
|:-------------------:|:-------:|:--------|
| 14.11.2022 | 1.7.7.9 | minor rtl edits and code optimizations; [#442](https://github.com/stnolting/neorv32/pull/442) |
| 05.11.2022 | 1.7.7.8 | minor rtl edits; [#441](https://github.com/stnolting/neorv32/pull/441) |
| 03.11.2022 | 1.7.7.7 | :sparkles: add fine-grained clock configuration for **TWI** module: add fine-grained clock configuration, add clock stretching configuration flag; [#440](https://github.com/stnolting/neorv32/pull/440) |
| 01.11.2022 | 1.7.7.6 | :warning: rework **SPI module**; [#438](https://github.com/stnolting/neorv32/pull/438) |
Expand Down
90 changes: 46 additions & 44 deletions rtl/core/neorv32_cpu_control.vhd
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Expand Up @@ -611,33 +611,29 @@ begin
begin
if rising_edge(clk_i) then
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
case opcode_v is -- save some bits here - the two LSBs are always "11" 32-bit instructions
case opcode_v is -- save some bits here - the two LSBs are always "11" for 32-bit instructions
when opcode_store_c => -- S-immediate: store
imm_o(XLEN-1 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
imm_o(00) <= execute_engine.i_reg(07);
imm_o(04 downto 00) <= execute_engine.i_reg(11 downto 07);
when opcode_branch_c => -- B-immediate: conditional branches
imm_o(XLEN-1 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
imm_o(11) <= execute_engine.i_reg(07);
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
imm_o(00) <= '0';
when opcode_lui_c | opcode_auipc_c => -- U-immediate: lui, auipc
imm_o(XLEN-1 downto 20) <= execute_engine.i_reg(31 downto 20);
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
imm_o(XLEN-1 downto 12) <= execute_engine.i_reg(31 downto 12);
imm_o(11 downto 00) <= (others => '0');
when opcode_jal_c => -- J-immediate: unconditional jumps
imm_o(XLEN-1 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
imm_o(11) <= execute_engine.i_reg(20);
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
imm_o(10 downto 01) <= execute_engine.i_reg(30 downto 21);
imm_o(00) <= '0';
when others => -- I-immediate: ALU-immediate, loads, jump-and-link with register
imm_o(XLEN-1 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
imm_o(10 downto 01) <= execute_engine.i_reg(30 downto 21);
imm_o(00) <= execute_engine.i_reg(20);
end case;
end if;
Expand Down Expand Up @@ -1065,11 +1061,13 @@ begin

when opcode_fence_c => -- fence operations
-- ------------------------------------------------------------
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c+1) = funct3_fence_c(2 downto 1)) then -- FENCE / FENCE.I
ctrl_nxt(ctrl_bus_fence_c) <= not execute_engine.i_reg(instr_funct3_lsb_c); -- FENCE
ctrl_nxt(ctrl_bus_fencei_c) <= execute_engine.i_reg(instr_funct3_lsb_c) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- FENCE.I
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then
ctrl_nxt(ctrl_bus_fence_c) <= '1'; -- FENCE
end if;
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then
ctrl_nxt(ctrl_bus_fencei_c) <= '1'; -- FENCE.I
end if;
execute_engine.state_nxt <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (PC <= PC)
execute_engine.state_nxt <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (= PC <= PC)


when opcode_fop_c => -- floating-point operations
Expand All @@ -1092,7 +1090,7 @@ begin
end if;


when others => -- opcode_system_c - environment operation / csr access / ILLEGAL OPCODE (will cause NO state change)
when opcode_system_c => -- environment operation / CSR access
-- ------------------------------------------------------------
csr.re_nxt <= '1'; -- always read CSR, only relevant for CSR access
if (CPU_EXTENSION_RISCV_Zicsr = true) then
Expand All @@ -1101,6 +1099,11 @@ begin
execute_engine.state_nxt <= DISPATCH;
end if;


when others => -- ILLEGAL OPCODE
-- ------------------------------------------------------------
execute_engine.state_nxt <= DISPATCH;

end case; -- /EXECUTE


Expand All @@ -1117,7 +1120,7 @@ begin
when funct12_dret_c => execute_engine.state_nxt <= TRAP_EXIT; debug_ctrl.dret <= '1'; -- dret
when others => execute_engine.sleep_nxt <= '1'; -- "funct12_wfi_c" - wfi/sleep
end case;
else -- CSR ACCESS - there will be no state change if illegal instruction
else -- CSR ACCESS - no CSR will be altered if illegal instruction
execute_engine.state_nxt <= DISPATCH;
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or -- CSRRW: always write CSR
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or -- CSRRWI: always write CSR
Expand Down Expand Up @@ -1880,12 +1883,11 @@ begin
end if;

-- --------------------------------------------------------------------
-- TRAP ENTER: write machine trap cause, PC and value register
-- TRAP ENTER
-- --------------------------------------------------------------------
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?

-- trap entry: write mcause, mepc and mtval --
-- > no update when in debug-mode!
-- NORMAL trap entry: write mcause, mepc and mtval - no update when in debug-mode! --
-- --------------------------------------------------------------------
if (CPU_EXTENSION_RISCV_DEBUG = false) or ((trap_ctrl.cause(5) = '0') and (debug_ctrl.running = '0')) then

Expand All @@ -1909,10 +1911,17 @@ begin
csr.mtval <= (others => '0');
end case;

-- update privilege level and interrupt enable stack --
csr.mstatus_mie <= '0'; -- disable interrupts
csr.mstatus_mpie <= csr.mstatus_mie; -- backup previous mie state
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
csr.mstatus_mpp <= csr.privilege; -- backup previous privilege mode
end if;

end if;

-- DEBUG MODE entry: write dpc and dcsr --
-- > no update when already in debug-mode!
-- DEBUG MODE entry: write dpc and dcsr - no update when already in debug-mode! --
-- --------------------------------------------------------------------
if (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.cause(5) = '1') and (debug_ctrl.running = '0') then

Expand All @@ -1931,39 +1940,30 @@ begin

end if;

end if;

-- --------------------------------------------------------------------
-- mstatus: context switch
-- TRAP EXIT
-- --------------------------------------------------------------------
-- ENTER: trap handler starting --
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
if (CPU_EXTENSION_RISCV_DEBUG = false) or -- normal trapping (debug mode NOT implemented)
((debug_ctrl.running = '0') and (trap_ctrl.cause(5) = '0')) then -- not IN debug mode and not ENTERING debug mode
csr.mstatus_mie <= '0'; -- disable interrupts
csr.mstatus_mpie <= csr.mstatus_mie; -- backup previous mie state
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
csr.mstatus_mpp <= csr.privilege; -- backup previous privilege mode
end if;
end if;
-- EXIT: return from trap --
elsif (trap_ctrl.env_end = '1') then
if (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') then -- return from debug mode
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented

-- return from debug mode --
if (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') then
if (CPU_EXTENSION_RISCV_U = true) then
csr.privilege <= csr.dcsr_prv;
end if;
else -- return from "normal trap"

-- return from "normal trap" --
else
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag
csr.mstatus_mpie <= '1';
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
if (CPU_EXTENSION_RISCV_U = true) then
csr.privilege <= csr.mstatus_mpp; -- restore previous privilege mode
csr.mstatus_mpp <= '0'; -- MRET has to clear mstatus.MPP
if (csr.mstatus_mpp /= priv_mode_m_c) then
csr.mstatus_mprv <= '0'; -- clear if return priv. mode is less than M
end if;
end if;
end if;

end if;

end if; -- /hardware csr access
Expand All @@ -1981,16 +1981,18 @@ begin

-- no user mode --
if (CPU_EXTENSION_RISCV_U = false) then
csr.mstatus_mpp <= '0';
csr.mstatus_mprv <= '0';
csr.mstatus_tw <= '0';
csr.privilege <= priv_mode_m_c;
--
csr.mstatus_mpp <= '0';
csr.mstatus_mprv <= '0';
csr.mstatus_tw <= '0';
--
csr.mcounteren_cy <= '0';
csr.mcounteren_tm <= '0';
csr.mcounteren_ir <= '0';
--
csr.dcsr_ebreaku <= '0';
csr.dcsr_prv <= '0';
csr.dcsr_ebreaku <= '0';
csr.dcsr_prv <= '0';
end if;

-- no PMP --
Expand Down
16 changes: 8 additions & 8 deletions rtl/core/neorv32_package.vhd
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Expand Up @@ -58,7 +58,7 @@ package neorv32_package is

-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070708"; -- NEORV32 version - no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070709"; -- NEORV32 version - no touchy!
constant archid_c : natural := 19; -- official RISC-V architecture ID - hands off!

-- Check if we're inside the Matrix -------------------------------------------------------
Expand Down Expand Up @@ -428,18 +428,18 @@ package neorv32_package is
-- RISC-V Opcodes -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- alu --
constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
constant opcode_auipc_c : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
constant opcode_alui_c : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
constant opcode_alu_c : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
constant opcode_auipc_c : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
-- control flow --
constant opcode_jal_c : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
constant opcode_jalr_c : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
-- memory access --
constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
-- system/csr --
-- sync/system/csr --
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
constant opcode_system_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
-- floating point operations --
Expand Down Expand Up @@ -855,10 +855,10 @@ package neorv32_package is
constant trap_firq14_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11110"; -- 1.30: fast interrupt 14
constant trap_firq15_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11111"; -- 1.31: fast interrupt 15
-- entering debug mode (sync./async. exceptions) --
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00001"; -- break instruction (sync)
constant trap_db_hw_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- hardware trigger (sync)
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async)
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async)
constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00001"; -- d.0.1: break instruction (sync)
constant trap_db_hw_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- d.0.2: hardware trigger (sync)
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- d.1.3: external halt request (async)
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- d.1.4: single-stepping (async)

-- CPU Trap System ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
Expand Down