Minor rtl edits and optimizations

[stnolting]

FIFO Component

• Add optional "outout gate": If OUT_GATE is enabled, the FIFO outputs all-zero if no valid data is available.

DMA

• Improve performance; now requires one cycle less for each read-write operation.
• Code cleanup and logic optimization.
• ⚠️ Rework "error"/"done" and interrupt acknowledge mechanism.

CoreMark

• 🧪 Add experimental multi-threading / dual-core configuration.