Make hardware breakpoint optional; constrain to debug-mode only

[stnolting]

• ✨ Add a new top generic to enable/disable the hardware-assisted breakpoint (RISC-V Sdtrig ISA extenion). A future PR might update this generic to specify a variable number of hardware triggers.

OCD_HW_BREAKPOINT : boolean := false; -- implement on-chip-debugger hardware breakpoint

• ⚠️ only allow debug-mode to use the trigger module; write accesses from machine_mode are ignore (tdata1.dmode CSR bit is hardwired to 1; simplifies trigger logic)
• ⚠️ the trigger action is constrained to "debug-mode entry" only (tdata1.action CSR bits are hardwired to 0001; simplifies trigger logic)