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⚠️✨ replace Zalrsc ISA extension by Zaamo ISA extension #1141

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merged 14 commits into from
Jan 4, 2025
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@stnolting stnolting commented Jan 3, 2025

⚠️ This PR removes support for the RISC-V Zalrsc ISA extension (reservation-set operations). Those operations were based on a single reservation set that provided very limited support for atomic memory accesses (e.g. for implementing spinlocks, semphores or mutexes).

✨ Therefore, this PR adds support for the RISC-V Zaamo ISA extension (atomic memory operations). This ISA extension adds actual atomic read-modify-write instructions to the core.

⚠️ Replace top generic: RISCV_ISA_Zalrsc -> RISCV_ISA_Zaamo

🧪 This is still highly experimental.

@stnolting stnolting added risc-v compliance Modification to comply with official RISC-V specs. HW Hardware-related labels Jan 3, 2025
@stnolting stnolting changed the title ⚠️ replace Zalrsc ISA extension by Zaamo ISA extension ⚠️✨ replace Zalrsc ISA extension by Zaamo ISA extension Jan 3, 2025
@stnolting stnolting marked this pull request as ready for review January 3, 2025 21:17
@stnolting stnolting mentioned this pull request Jan 3, 2025
@stnolting stnolting merged commit 651732d into main Jan 4, 2025
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@stnolting stnolting deleted the amo branch January 4, 2025 05:22
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