[vivado ip] make m_axi (XBUS) interface optional

[donlon]

Hey thank you for merging my recent pulls! And here's the last split of #1060.

As mentioned in #1060 (comment) did you encounter any error from the tool? It works fine for me on my computer with Vivado 2022.2.

[stnolting]

When I disable the XBUS interface the according input ports are terminated according to the VHDL defaults. However, in my (auto-generated) VHDL top wrapper this is done in a "Verilog style" (using a literal) instead of using VHDL's (others => '0') statement:

This is one of the faulting lines:

m_axi_rresp => X"3",

m_axi_rresp is only 2-bits wide, but X"3" implies a 4-bit width.

Are you using a Verilog top wrapper?

[stnolting]

I just removed the default values for AXI ports whose bit-width is not 1 or a power of two and this seems to fix this issue. 🚀

[stnolting]

This seems ready from my side. @donlon can you have another look at it?

[donlon]

Oops forget to synthesize the generated core...My Vivado also generate the same wrapper that results in the width mismatch errors, and removing these default values does fix, which looks like a bug of Vivado. I think it's good and ready to go now!

[stnolting]

Thanks for the feedback!