⚠️ Remove OCD's DM legacy mode

CHANGELOG.md

@@ -29,7 +29,8 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
-| 11.10.2024 | 1.10.5.5 | :sparkles: :lock: add optional support for on-chip debugger authentication; :warning: rename OCD-related top generics | [#](https://github.com/stnolting/neorv32/pull/1053) |
+| 12.10.2024 | 1.10.5.6 | :warning: remove legacy support for on-chip debugger DM version v0.13; now only supporting DM v1.0 (removing `OCD_DM_LEGACY_MODE` generic) | [#1056](https://github.com/stnolting/neorv32/pull/1056) |
+| 11.10.2024 | 1.10.5.5 | :sparkles: :lock: add support for optional on-chip debugger authentication; :warning: rename OCD-related top generics | [#1053](https://github.com/stnolting/neorv32/pull/1053) |
 | 06.10.2024 | 1.10.5.4 | :warning: rework PWM module | [#1049](https://github.com/stnolting/neorv32/pull/1049) |
 | 05.10.2024 | 1.10.5.3 | upgrade neoTRNG to version 3.2 | [#1048](https://github.com/stnolting/neorv32/pull/1048) |
 | 03.10.2024 | 1.10.5.2 | :warning: remove `A` ISA extensions; replaced by new `Zalrsc` ISA extension | [#1047](https://github.com/stnolting/neorv32/pull/1047) |

docs/datasheet/on_chip_debugger.adoc

@@ -158,8 +158,7 @@ single hart and provides the following architectural core features:
 
 .DM Spec. Version
 [TIP]
-By default, the OCD's debug module supports version 1.0 of the RISC-V debug spec. However, for backwards compatibility the
-DM can be downgraded back to version 0.13 via the see <<_processor_top_entity_generics, `OCD_DM_LEGACY_MODE`>> top generic.
+The NEORV32 DM complies to the RISC-V DM spec version 1.0.
 
 From the DTM's point of view, the DM implements a set of <<_dm_registers>> that are used to control and monitor the
 debugging session. From the CPU's point of view, the DM implements several memory-mapped registers that are used for
@@ -192,8 +191,7 @@ to these registers will always return zero.
 | 0x20    | <<_progbuf, `progbuf0`>> | Program buffer 0
 | 0x21    | <<_progbuf, `progbuf1`>> | Program buffer 1
 | 0x30    | <<_authdata>>            | Data to/from the authentication module
-| 0x38    | `sbcs`                   | System bus access control and status; reads as zero to indicate there is **no** direct system bus access
-| 0x40    | <<_haltsum0>>            | Halted harts
+| 0x38    | `sbcs`                   | System bus access control and status; reads as zero to indicate there is **no** system bus access
 |=======================
 
 
@@ -269,7 +267,7 @@ are configured as "zero" and are read-only. Writing '1' to these bits/fields wil
 |  6    | `authbusy`        | set if authentication is busy, see <<_debug_authentication>>
 |  5    | `hasresethaltreq` | `0`: halt-on-reset is not supported (directly)
 |  4    | `confstrptrvalid` | `0`: no configuration string available
-| 3:0   | `version`         | debug spec. version; `0011` (v1.0) or `0010` (v0.13); configured via the <<_processor_top_entity_generics, `OCD_DM_LEGACY_MODE`>> top generic
+| 3:0   | `version`         | `0011`: DM compatible to debug spec. version v1.0
 |=======================
 
 
@@ -412,27 +410,6 @@ hart's GPRs x0 - x15/31 (abstract command register index `0x1000` - `0x101f`).
 |======
 
 
-
-:sectnums!:
-===== **`haltsum0`**
-
-[cols="4,27,>7"]
-[frame="topbot",grid="none"]
-|======
-| 0x408 | **Halted harts status** | `haltsum0`
-3+| Reset value: `0x00000000`
-3+| Hart has halted when according bit is set.
-|======
-
-.`haltsum0` Register Bits
-[cols="^1,^2,^1,<8"]
-[options="header",grid="rows"]
-|=======================
-| Bit | Name [RISC-V] | R/W | Description
-| 0   | `haltsum0[0]` | r/- | Hart is halted when set.
-|=======================
-
-
 :sectnums:
 ==== DM CPU Access
 

docs/datasheet/soc.adoc

@@ -210,7 +210,6 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 | `JEDEC_ID`              | suv(10:0) | 0b00000000000 | JEDEC ID; continuation codes plus vendor ID (passed to <<_mvendorid>> CSR and to the <<_debug_transport_module_dtm>>).
 4+^| **<<_on_chip_debugger_ocd>>**
 | `OCD_EN`                | boolean   | false         | Implement the on-chip debugger and the CPU debug mode.
-| `OCD_DM_LEGACY_MODE`    | boolean   | false         | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode).
 | `OCD_AUTHENTICATION`    | boolean   | false         | Implement <<_debug_authentication>> module.
 4+^| **CPU <<_instruction_sets_and_extensions>>**
 | `RISCV_ISA_C`           | boolean   | false         | Enable <<_c_isa_extension>> (compressed instructions).

rtl/core/neorv32_debug_dm.vhd

@@ -20,7 +20,6 @@ use neorv32.neorv32_package.all;
 entity neorv32_debug_dm is
   generic (
     CPU_BASE_ADDR : std_ulogic_vector(31 downto 0); -- base address for the memory-mapped CPU interface registers
-    LEGACY_MODE   : boolean; -- false = spec. v1.0, true = spec. v0.13
     AUTHENTICATOR : boolean -- implement authentication module when true
   );
   port (
@@ -66,12 +65,11 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is
   constant addr_abstractcs_c   : std_ulogic_vector(6 downto 0) := "0010110";
   constant addr_command_c      : std_ulogic_vector(6 downto 0) := "0010111";
   constant addr_abstractauto_c : std_ulogic_vector(6 downto 0) := "0011000";
-  constant addr_nextdm_c       : std_ulogic_vector(6 downto 0) := "0011101";
+--constant addr_nextdm_c       : std_ulogic_vector(6 downto 0) := "0011101"; -- hardwired to zero
   constant addr_progbuf0_c     : std_ulogic_vector(6 downto 0) := "0100000";
   constant addr_progbuf1_c     : std_ulogic_vector(6 downto 0) := "0100001";
   constant addr_authdata_c     : std_ulogic_vector(6 downto 0) := "0110000";
-  constant addr_sbcs_c         : std_ulogic_vector(6 downto 0) := "0111000";
-  constant addr_haltsum0_c     : std_ulogic_vector(6 downto 0) := "1000000";
+--constant addr_sbcs_c         : std_ulogic_vector(6 downto 0) := "0111000"; -- hardwired to zero
 
   -- DMI access --
   signal dmi_wren, dmi_wren_auth, dmi_rden, dmi_rden_auth : std_ulogic;
@@ -106,8 +104,7 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is
   -- ----------------------------------------------------------
 
   -- DM configuration --
-  constant dataaddr_c   : std_ulogic_vector(11 downto 0) := dm_data_base_c(11 downto 0); -- signed base address of data registers in memory/CSR space
-  constant dm_version_c : std_ulogic_vector(3 downto 0)  := cond_sel_suv_f(LEGACY_MODE, "0010", "0011"); -- version: v0.13 / v1.0
+  constant dataaddr_c : std_ulogic_vector(11 downto 0) := dm_data_base_c(11 downto 0); -- signed base address of data registers in memory/CSR space
 
   -- debug module controller --
   type dm_ctrl_state_t is (CMD_IDLE, CMD_CHECK, CMD_PREPARE, CMD_TRIGGER, CMD_BUSY, CMD_ERROR);
@@ -192,13 +189,6 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is
 
 begin
 
-  -- Configuration Info ---------------------------------------------------------------------
-  -- -------------------------------------------------------------------------------------------
-  assert not (LEGACY_MODE   = true)  report "[NEORV32] OCD: DM compatible to debug spec. version 0.13" severity note;
-  assert not (LEGACY_MODE   = false) report "[NEORV32] OCD: DM compatible to debug spec. version 1.0"  severity note;
-  assert not (AUTHENTICATOR = false) report "[NEORV32] OCD: authentication enabled."  severity note;
-
-
   -- DMI Access -----------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   -- any access --
@@ -227,7 +217,6 @@ begin
         dm_ctrl.ldsw_progbuf  <= instr_sw_c;
         dci.execute_req       <= '0';
         dm_ctrl.pbuf_en       <= '0';
-        --
         dm_ctrl.illegal_cmd   <= '0';
         dm_ctrl.illegal_state <= '0';
         dm_ctrl.cmderr        <= (others => '0');
@@ -273,7 +262,7 @@ begin
 
           when CMD_PREPARE => -- setup program buffer
           -- ------------------------------------------------------------
-            if (dm_reg.command(17) = '1') then -- "transfer"
+            if (dm_reg.command(17) = '1') then -- "transfer" (GPR <-> DM.data0)
               if (dm_reg.command(16) = '0') then -- "write" = 0 -> read from GPR
                 dm_ctrl.ldsw_progbuf <= instr_sw_c;
                 dm_ctrl.ldsw_progbuf(31 downto 25) <= dataaddr_c(11 downto 5); -- destination address
@@ -347,41 +336,36 @@ begin
       dm_ctrl.hart_resume_ack <= '0';
       dm_ctrl.hart_reset      <= '0';
     elsif rising_edge(clk_i) then
-
-      -- HALTED ACK --
+      -- halted ACK --
       if (dm_reg.dmcontrol_ndmreset = '1') then
         dm_ctrl.hart_halted <= '0';
       elsif (dci.halt_ack = '1') then
         dm_ctrl.hart_halted <= '1';
       elsif (dci.resume_ack = '1') then
         dm_ctrl.hart_halted <= '0';
       end if;
-
-      -- RESUME REQ --
+      -- resume REQ --
       if (dm_reg.dmcontrol_ndmreset = '1') then
         dm_ctrl.hart_resume_req <= '0';
       elsif (dm_reg.resume_req = '1') then
         dm_ctrl.hart_resume_req <= '1';
       elsif (dci.resume_ack = '1') then
         dm_ctrl.hart_resume_req <= '0';
       end if;
-
-      -- RESUME ACK --
+      -- resume ACK --
       if (dm_reg.dmcontrol_ndmreset = '1') then
         dm_ctrl.hart_resume_ack <= '0';
       elsif (dci.resume_ack = '1') then
         dm_ctrl.hart_resume_ack <= '1';
       elsif (dm_reg.resume_req = '1') then
         dm_ctrl.hart_resume_ack <= '0';
       end if;
-
-      -- hart has been RESET --
+      -- reset ACK --
       if (dm_reg.dmcontrol_ndmreset = '1') then -- explicit RESET triggered by DM
         dm_ctrl.hart_reset <= '1';
       elsif (dm_reg.reset_ack = '1') then
         dm_ctrl.hart_reset <= '0';
       end if;
-
     end if;
   end process hart_status;
 
@@ -489,7 +473,7 @@ begin
   cpu_ndmrstn_o <= '0' when (dm_reg.dmcontrol_ndmreset = '1') and (dm_reg.dmcontrol_dmactive = '1') and ((not AUTHENTICATOR) or (auth.valid = '1')) else '1';
 
   -- construct program buffer array for CPU access --
-  cpu_progbuf(0) <= dm_ctrl.ldsw_progbuf; -- pseudo program buffer for GPR access
+  cpu_progbuf(0) <= dm_ctrl.ldsw_progbuf; -- pseudo program buffer for GPR<->DM.data0 transfer
   cpu_progbuf(1) <= instr_nop_c when (dm_ctrl.pbuf_en = '0') else dm_reg.progbuf(0);
   cpu_progbuf(2) <= instr_nop_c when (dm_ctrl.pbuf_en = '0') else dm_reg.progbuf(1);
   cpu_progbuf(3) <= instr_ebreak_c; -- implicit ebreak instruction
@@ -530,9 +514,9 @@ begin
             dmi_rsp_o.data(5)            <= '0';                       -- hasresethaltreq (r/-): halt-on-reset not implemented
             dmi_rsp_o.data(4)            <= '0';                       -- confstrptrvalid (r/-): no configuration string available
           end if;
-         dmi_rsp_o.data(7)          <= auth.valid;   -- authenticated (r/-): authentication successful when set
-         dmi_rsp_o.data(6)          <= auth.busy;    -- authbusy (r/-): wait for authenticator operation when set
-         dmi_rsp_o.data(3 downto 0) <= dm_version_c; -- version (r/-): DM spec. version
+         dmi_rsp_o.data(7)          <= auth.valid; -- authenticated (r/-): authentication successful when set
+         dmi_rsp_o.data(6)          <= auth.busy;  -- authbusy (r/-): wait for authenticator operation when set
+         dmi_rsp_o.data(3 downto 0) <= "0011";     -- version (r/-): DM spec. version v1.0
 
         -- debug module control --
         when addr_dmcontrol_c =>
@@ -589,34 +573,18 @@ begin
             dmi_rsp_o.data <= dci.data_reg;
           end if;
 
-        -- program buffer 0 --
-        when addr_progbuf0_c =>
-          if (not AUTHENTICATOR) or (auth.valid = '1') then -- authenticated?
-            if LEGACY_MODE then
-              dmi_rsp_o.data <= dm_reg.progbuf(0);
-            end if;
-          end if;
-
-        -- program buffer 1 --
-        when addr_progbuf1_c =>
-          if (not AUTHENTICATOR) or (auth.valid = '1') then -- authenticated?
-            if LEGACY_MODE then
-              dmi_rsp_o.data <= dm_reg.progbuf(1);
-            end if;
-          end if;
-
         -- authentication --
         when addr_authdata_c =>
           dmi_rsp_o.data <= auth.rdata;
 
-        -- halt summary 0 --
-        when addr_haltsum0_c =>
-          if (not AUTHENTICATOR) or (auth.valid = '1') then -- authenticated?
-            dmi_rsp_o.data(0) <= dm_ctrl.hart_halted; -- hart 0 is halted
-          end if;
+--      -- halt summary 0 (not required for DM spec. v1.0 if there is only a single hart) --
+--      when "1000000" => -- haltsum0
+--        if (not AUTHENTICATOR) or (auth.valid = '1') then -- authenticated?
+--          dmi_rsp_o.data(0) <= dm_ctrl.hart_halted; -- hart 0 is halted
+--        end if;
 
         -- not implemented or read-only-zero --
-        when others => -- addr_sbcs_c, addr_nextdm_c, addr_command_c
+        when others => -- addr_sbcs_c, addr_progbuf0_c, addr_progbuf1_c, addr_nextdm_c, addr_command_c
           dmi_rsp_o.data <= (others => '0');
 
       end case;
@@ -627,7 +595,7 @@ begin
          ((dmi_req_i.addr = addr_data0_c) or (dmi_req_i.addr = addr_progbuf0_c) or (dmi_req_i.addr = addr_progbuf1_c)) then
         dm_reg.rd_acc_err <= '1';
       else
-        dm_reg.rd_acc_err  <= '0';
+        dm_reg.rd_acc_err <= '0';
       end if;
 
       -- auto execution trigger --

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100505"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100506"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -123,7 +123,6 @@ package neorv32_package is
   -- -------------------------------------------------------------------------------------------
   -- bus request --
   type bus_req_t is record
-    -- in-band signals --
     addr  : std_ulogic_vector(31 downto 0); -- access address
     data  : std_ulogic_vector(31 downto 0); -- write data
     ben   : std_ulogic_vector(3 downto 0); -- byte enable
@@ -132,8 +131,7 @@ package neorv32_package is
     src   : std_ulogic; -- access source (1=instruction fetch, 0=data access)
     priv  : std_ulogic; -- set if privileged (machine-mode) access
     rvso  : std_ulogic; -- set if reservation set operation (atomic LR/SC)
-    -- out-of-band signals --
-    fence : std_ulogic; -- set if fence(.i) operation, single-shot
+    fence : std_ulogic; -- set if fence(.i) operation, single-shot (out-of-band)
   end record;
 
   -- bus response --
@@ -677,7 +675,6 @@ package neorv32_package is
       INT_BOOTLOADER_EN     : boolean                        := false;
       -- On-Chip Debugger (OCD) --
       OCD_EN                : boolean                        := false;
-      OCD_DM_LEGACY_MODE    : boolean                        := false;
       OCD_AUTHENTICATION    : boolean                        := false;
       -- RISC-V CPU Extensions --
       RISCV_ISA_C           : boolean                        := false;