Merge pull request #366 from stnolting/csr_reset

[rtl] reset all "core" CSRs to zero

CHANGELOG.md

@@ -32,6 +32,7 @@ mimpid = 0x01040312 => 01.04.03.12 => Version 01.04.03.12 => v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 14.07.2022 | 1.7.3.11 | reset all "core" CSRs to all-zero; [#366](https://github.com/stnolting/neorv32/pull/366) |
 | 13.07.2022 | 1.7.3.10 | :bug: reworked/fixed **physical memory protection**; :sparkles: added `mstatus.MPRV` flag; [#365](https://github.com/stnolting/neorv32/pull/365) |
 | 12.07.2022 | 1.7.3.9 | clean-up and rework **bootloader**; :sparkles: add "boot via XIP" option; [#364](https://github.com/stnolting/neorv32/pull/364) |
 | 11.07.2022 | 1.7.3.8 | **physical memory protection(PMP)**: locking entry `i` in TOR mode will now also prevent write access to `pmpaddr(i-1)` (RISC-V compatibility); [#363](https://github.com/stnolting/neorv32/pull/363) |

docs/datasheet/cpu.adoc

@@ -999,7 +999,7 @@ memory system to perform the necessary operations (for example a cache flush and
 In order to reduce routing constraints (and by this the actual hardware requirements), most uncritical
 registers of the NEORV32 CPU as well as most register of the whole NEORV32 Processor do not use **a
 dedicated hardware reset**. "Uncritical registers" in this context means that the initial value of these registers
-after power-up is not relevant for a defined CPU boot process.
+after power-up/reset is not relevant for a defined CPU boot process.
 
 
 **Rationale**
@@ -1016,26 +1016,19 @@ this example "uncritical registers".
 
 **NEORV32 CPU Reset**
 
-In terms of the NEORV32 CPU, there are several pipeline registers, state machine registers and even status
+In terms of the NEORV32 CPU, there are several pipeline registers, state machine registers and even some status
 and control registers (CSRs) that do not require a defined initial state to ensure a correct boot process. The
 pipeline register will get initialized by the CPU's internal state machines, which are initialized from the main
-control engine that actually features a defined reset. The initialization of most of the CPU's core CSRs (like
-interrupt control) is done by the software (to be more specific, this is done by the `crt0.S` start-up code).
-
-During the very early boot process (where `crt0.S` is running) there is no chance for undefined behavior due to
-the lack of dedicated hardware resets of certain CSRs. For example the machine interrupt-enable CSR <<_mie>>
-does not provide a dedicated reset. The value after reset of this register is uncritical as interrupts cannot fire
-because the global interrupt enabled flag in the status register (`mstatsus(mie)`) _do_ provide a dedicated
-hardware reset setting this bit to low (globally disabling interrupts).
+control engine that actually features a defined reset.
 
 
 **Reset Configuration**
 
 Most CPU-internal register do provide an asynchronous reset in the VHDL code, but the "don't care" value
-(VHDL `'-'`) is used for initialization of all uncritical registers, effectively generating a flip-flop without a
+(VHDL `'-'`) is used for initialization of all uncritical registers - effectively generating a flip-flop without a
 reset. However, certain applications or situations (like advanced gate-level / timing simulations) might
-require a more deterministic reset state. For this case, a defined reset level (reset-to-low) of all CPU registers can
-be enabled by enabling a constant in the main VHDL package file (`rtl/core/neorv32_package.vhd`):
+require a more deterministic reset state. For this case, a defined reset level (reset-to-low) of most CPU registers can
+be configured by enabling a constant in the main VHDL package file (`rtl/core/neorv32_package.vhd`):
 
 [source,vhdl]
 ----

docs/datasheet/on_chip_debugger.adoc

@@ -214,7 +214,7 @@ their functionality.
 [frame="topbot",grid="none"]
 |======
 | 0x04 | **Abstract data 0** | `data0`
-3+| Reset value: _UNDEFINED_
+3+| Reset value: `UNDEFINED`
 3+| Basic read/write registers to be used with abstract command (for example to read/write data from/to CPU GPRs).
 |======
 
@@ -226,7 +226,7 @@ their functionality.
 [frame="topbot",grid="none"]
 |======
 | 0x10 | **Debug module control register** | `dmcontrol`
-3+| Reset value: 0x00000000
+3+| Reset value: `0x00000000`
 3+| Control of the overall debug module and the hart. The following table shows all implemented bits. All remaining bits/bit-fields are configures as "zero" and are
 read-only. Writing '1' to these bits/fields will be ignored.
 |======
@@ -251,7 +251,7 @@ read-only. Writing '1' to these bits/fields will be ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x11 | **Debug module status register** | `dmstatus`
-3+| Reset value: 0x00000000
+3+| Reset value: `0x00400082`
 3+| Current status of the overall debug module and the hart. The entire register is read-only.
 |======
 
@@ -290,7 +290,7 @@ read-only. Writing '1' to these bits/fields will be ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x12 | **Hart information** | `hartinfo`
-3+| Reset value: see below
+3+| Reset value: _see below_
 3+| This register gives information about the hart. The entire register is read-only.
 |======
 
@@ -315,7 +315,7 @@ read-only. Writing '1' to these bits/fields will be ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x16 | **Abstract control and status** | `abstracts`
-3+| Reset value: see below
+3+| Reset value: _see below_
 3+| Command execution info and status.
 |======
 
@@ -350,7 +350,7 @@ Error codes in `cmderr` (highest priority first):
 [frame="topbot",grid="none"]
 |======
 | 0x17 | **Abstract command** | `command`
-3+| Reset value: 0x00000000
+3+| Reset value: `0x00000000`
 3+| Writing this register will trigger the execution of an abstract command. New command can only be executed if
 `cmderr` is zero. The entire register in write-only (reads will return zero).
 |======
@@ -382,7 +382,7 @@ hart's GPRs (abstract command register index `0x1000` - `0x101f`).
 [frame="topbot",grid="none"]
 |======
 | 0x18 | **Abstract command auto-execution** | `abstractauto`
-3+| Reset value: 0x00000000s
+3+| Reset value: `0x00000000`
 3+| Register to configure when a read/write access to a DM repeats execution of the last abstract command.
 |======
 
@@ -417,7 +417,7 @@ hart's GPRs (abstract command register index `0x1000` - `0x101f`).
 [frame="topbot",grid="none"]
 |======
 | 0x40 | **Halt summary 0** | `haltsum0`
-3+| Reset value: _UNDEFINED_
+3+| Reset value: `UNDEFINED`
 3+| Bit 0 of this register is set if the hart is halted (all remaining bits are always zero). The entire register is read-only.
 |======
 
@@ -578,7 +578,7 @@ is raised.
 [frame="topbot",grid="none"]
 |======
 | 0x7b0 | **Debug control and status register** | `dcsr`
-3+| Reset value: 0x40000000
+3+| Reset value: `0x40000403`
 3+| The `dcsr` CSR is compatible to the RISC-V debug spec. It is used to configure debug mode and provides additional status information.
 The following bits are implemented. The reaming bits are read-only and always read as zero.
 |======
@@ -620,7 +620,7 @@ Cause codes in `dcsr.cause` (highest priority first):
 [frame="topbot",grid="none"]
 |======
 | 0x7b1 | **Debug program counter** | `dpc`
-3+| Reset value: _UNDEFINED_
+3+| Reset value: `0x00000000`
 3+| The `dcsr` CSR is compatible to the RISC-V debug spec. It is used to store the current program counter when
 debug mode is entered. The `dret` instruction will return to `dpc` by moving `dpc` to `pc`.
 |======
@@ -633,7 +633,7 @@ debug mode is entered. The `dret` instruction will return to `dpc` by moving `dp
 [frame="topbot",grid="none"]
 |======
 | 0x7b2 | **Debug scratch register 0** | `dscratch0`
-3+| Reset value: _UNDEFINED_
+3+| Reset value: `0x00000000`
 3+| The `dscratch0` CSR is compatible to the RISC-V debug spec. It provides a general purpose debug mode-only scratch register.
 |======
 
@@ -674,7 +674,7 @@ Hence, the CSRs of this module are only relevant for the debugger.
 [frame="topbot",grid="none"]
 |======
 | 0x7a0 | **Trigger select register** | `tselect`
-3+| Reset value: 0x00000000
+3+| Reset value: `0x00000000`
 3+| This CSR is hardwired to zero indicating there is only one trigger available. Any write access is ignored.
 |======
 
@@ -686,7 +686,7 @@ Hence, the CSRs of this module are only relevant for the debugger.
 [frame="topbot",grid="none"]
 |======
 | 0x7a1 | **Trigger data register 1 / match control register** | `tdata1` / `mcontrol`
-3+| Reset value: 0x28041048
+3+| Reset value: `0x28041048`
 3+| This CSR is used to configure the address match trigger. Only one bit is writable, the remaining bits are hardwired (see table below).
 Write attempts to the hardwired bits are ignored.
 |======
@@ -723,7 +723,7 @@ Write attempts to the hardwired bits are ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x7a2 | **Trigger data register 2** | `tdata2`
-3+| Reset value: _UNDEFINED_
+3+| Reset value: `0x00000000`
 3+| Since only the "address match trigger" type is supported, this r/w CSR is used to store the address of the triggering instruction.
 |======
 
@@ -735,7 +735,7 @@ Write attempts to the hardwired bits are ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x7a3 | **Trigger data register 3** | `tdata3`
-3+| Reset value: 0x00000000
+3+| Reset value: `0x00000000`
 3+| This CSR is not required for the NEORV32 trigger module. Hence, it is hardwired to zero and any write access is ignored.
 |======
 
@@ -747,7 +747,7 @@ Write attempts to the hardwired bits are ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x7a4 | **Trigger information register** | `tinfo`
-3+| Reset value: 0x00000004
+3+| Reset value: `0x00000004`
 3+| This CSR is hardwired to "4" indicating there is only an "address match trigger" available. Any write access is ignored.
 |======
 
@@ -759,7 +759,7 @@ Write attempts to the hardwired bits are ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x7a5 | **Trigger control register** | `tcontrol`
-3+| Reset value: 0x00000000
+3+| Reset value: `0x00000000`
 3+| This CSR is not required for the NEORV32 trigger module. Hence, it is hardwired to zero and any write access is ignored.
 |======
 
@@ -771,7 +771,7 @@ Write attempts to the hardwired bits are ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x7a8 | **Machine context register** | `mcontext`
-3+| Reset value: 0x00000000
+3+| Reset value: `0x00000000`
 3+| This CSR is not required for the NEORV32 trigger module. Hence, it is hardwired to zero and any write access is ignored.
 |======
 
@@ -783,7 +783,7 @@ Write attempts to the hardwired bits are ignored.
 [frame="topbot",grid="none"]
 |======
 | 0x7aa | **Supervisor context register** | `scontext`
-3+| Reset value: 0x00000000
+3+| Reset value: `0x00000000`
 3+| This CSR is not required for the NEORV32 trigger module. Hence, it is hardwired to zero and any write access is ignored.
 |======
 

rtl/core/neorv32_application_image.vhd

@@ -1,8 +1,8 @@
 -- The NEORV32 RISC-V Processor: https://github.com/stnolting/neorv32
 -- Auto-generated memory initialization file (for APPLICATION) from source file <blink_led/main.bin>
--- Size: 1032 bytes
+-- Size: 1020 bytes
 -- MARCH: default
--- Built: 08.07.2022 14:57:32
+-- Built: 14.07.2022 15:09:04
 
 -- prototype defined in 'neorv32_package.vhd'
 package body neorv32_application_image is
@@ -14,12 +14,9 @@ x"ff810113",
 x"80000197",
 x"7f418193",
 x"00000517",
-x"13c50513",
+x"13050513",
 x"30551073",
-x"34151073",
-x"000023b7",
-x"80038393",
-x"30039073",
+x"30001073",
 x"30401073",
 x"34401073",
 x"32001073",
@@ -28,10 +25,10 @@ x"b0001073",
 x"b8001073",
 x"b0201073",
 x"b8201073",
-x"00000093",
 x"00000213",
 x"00000293",
 x"00000313",
+x"00000393",
 x"00000813",
 x"00000893",
 x"00000913",
@@ -48,11 +45,11 @@ x"00000e13",
 x"00000e93",
 x"00000f13",
 x"00000f93",
-x"40800593",
+x"3fc00593",
 x"80000617",
-x"f5c60613",
+x"f6860613",
 x"80000697",
-x"f5468693",
+x"f6068693",
 x"00c58e63",
 x"00d65c63",
 x"0005a703",
@@ -61,15 +58,15 @@ x"00458593",
 x"00460613",
 x"fedff06f",
 x"80000717",
-x"f3070713",
+x"f3c70713",
 x"80000797",
-x"f2878793",
+x"f3478793",
 x"00f75863",
 x"00072023",
 x"00470713",
 x"ff5ff06f",
-x"40800413",
-x"40800493",
+x"3fc00413",
+x"3fc00493",
 x"00945a63",
 x"0009a083",
 x"000080e7",
@@ -80,12 +77,12 @@ x"00000593",
 x"088000ef",
 x"30047073",
 x"34051073",
-x"40800993",
-x"40800a13",
-x"0149da63",
-x"0009a303",
-x"000300e7",
-x"00498993",
+x"3fc00413",
+x"3fc00493",
+x"00945a63",
+x"00042083",
+x"000080e7",
+x"00440413",
 x"ff1ff06f",
 x"00000093",
 x"00008463",
@@ -116,49 +113,45 @@ x"00000513",
 x"00000593",
 x"00112623",
 x"00812423",
-x"03c000ef",
+x"0e0000ef",
 x"00000513",
 x"00150413",
 x"00000593",
 x"0ff57513",
-x"028000ef",
+x"0cc000ef",
 x"10000513",
-x"030000ef",
+x"020000ef",
 x"00040513",
 x"fe5ff06f",
 x"f9402583",
 x"f9002503",
 x"f9402783",
 x"fef59ae3",
 x"00008067",
-x"fc000793",
-x"00a7a423",
-x"00b7a623",
-x"00008067",
 x"fe010113",
 x"00a12623",
 x"fe002503",
 x"3e800593",
 x"00112e23",
 x"00812c23",
 x"00912a23",
-x"144000ef",
+x"154000ef",
 x"00c12603",
 x"00000693",
 x"00000593",
-x"09c000ef",
+x"0ac000ef",
 x"fe802783",
 x"00020737",
 x"00050413",
 x"00e7f7b3",
 x"00058493",
 x"02078e63",
-x"f95ff0ef",
+x"fa5ff0ef",
 x"00850433",
 x"00a43533",
 x"009584b3",
 x"009504b3",
-x"f81ff0ef",
+x"f91ff0ef",
 x"fe95eee3",
 x"00b49463",
 x"fe856ae3",
@@ -176,6 +169,10 @@ x"fff50513",
 x"00000013",
 x"ff1ff06f",
 x"fcdff06f",
+x"fc000793",
+x"00a7a423",
+x"00b7a623",
+x"00008067",
 x"00050613",
 x"00000513",
 x"0015f693",