[docs] minor edits

docs/datasheet/cpu_dual_core.adoc

@@ -45,7 +45,7 @@ sections at boot-up.
 (see section <<_c_standard_library>>).
 | **Cache coherency** | Be aware that there is no cache snooping available. If any level-1 cache is enabled
 (<<_processor_internal_instruction_cache_icache>> and/or <<_processor_internal_data_cache_dcache>>) care
-must be taken to prevent access to outdated data - either by using cache synchronization (`fence[.]`
+must be taken to prevent access to outdated data - either by using cache synchronization (`fence` / `fence.i`
 instructions) or by using <<_atomic_memory_access>>.
 | **Inter-core communication** | See section <<_inter_core_communication_icc>>.
 | **Bootloader** | Only core 0 will boot and execute the bootloader while core 1 is held in standby.

docs/datasheet/soc_clint.adoc

@@ -56,6 +56,9 @@ machine software interrupt become available as processor-external signals (`mtim
 | Address      | Name [C]      | Bits | R/W | Function
 .2+<| `0xfff40000` .2+<| `MSWI[0]` ^| 0    ^| r/w <| trigger machine software interrupt for hart 0 when set
                                    ^| 31:1 ^| r/- <| hardwired to zero
+.2+<| `0xfff40004` .2+<| `MSWI[1]` ^| 0    ^| r/w <| trigger machine software interrupt for hart 1 when set
+                                   ^| 31:1 ^| r/- <| hardwired to zero
 | `0xfff44000` | `MTIMECMP[0]` | 63:0 | r/w | 64-bit time compare for hart 0
+| `0xfff44008` | `MTIMECMP[1]` | 63:0 | r/w | 64-bit time compare for hart 1
 | `0xfff4bff8` | `MTIME`       | 63:0 | r/w | 64-bit global machine timer
 |=======================