[docs] clean up reset sections

docs/datasheet/cpu.adoc

@@ -1073,25 +1073,3 @@ bit) and word (= 32-bit) boundaries, but not all processor module support sub-wo
 Whenever the CPU executes a `fence` instruction, the according interface signal is set high for one cycle
 (`d_bus_fence_o` for a `fence` instruction; `i_bus_fence_o` for a `fence.i` instruction). It is the task of the
 memory system to perform the necessary operations (for example a cache flush/reload).
-
-
-
-<<<
-// ####################################################################################################################
-:sectnums:
-==== CPU Hardware Reset
-
-In order to reduce routing constraints (and by this the actual hardware requirements), most _uncritical registers_
-of the NEORV32 CPU as well as most registers of the whole NEORV32 Processor do not use **a dedicated hardware reset**.
-"Uncritical registers" in this context means that the initial value of the according register(s)
-after power-up/reset is not relevant for a defined CPU boot/start process.
-
-Many CPU-internal register do provide an asynchronous reset described in the VHDL code, but the "don't care" value
-(VHDL `'-'`) is used for initialization of uncritical registers - effectively generating a flip-flop without a
-reset input.
-
-In terms of the NEORV32 CPU, there are several pipeline registers, state machine registers and even some status
-and control registers (CSRs) that do not require a defined initial state to ensure a correct boot process. The
-pipeline register will get initialized by the CPU's internal state machines, which are initialized from the main
-control engine that actually features a defined hardware reset.
-

docs/datasheet/soc.adoc

@@ -1125,29 +1125,42 @@ _enable_ bit in the according module's control register), it is automatically de
 :sectnums:
 === Processor Reset
 
-The processor provides two reset systems: an _external_ one and an _internal_ one. The external reset is triggered by
-the asynchronous, low-active `rstn_i` top entity signal. The internal reset is a synchronous, low-active reset that
-can be triggered by the external reset, the <<_on_chip_debugger_ocd>> and the <<_watchdog_timer_wdt>>.
-
-If the external hardware reset (`rstn_i`) is active it will be _asynchronously_ applied to all processor modules. An
-internal shift register ensures that the system wide reset will be active for at least 4 clock cycles. After that,
-the system wide reset is de-asserted _synchronously_ at a _falling_ edge of the main clock to ensure there are no
-meta-stable situation (like de-asserting reset at a rising edge).
-
-If one of the internal reset sources trigger a reset, this will be applied _synchronously_ to all processor modules
-at a rising edge. This signal is also extended to be active for at least 4 clock cycles. After that, the system wide
-reset is also de-asserted _synchronously_ at a _falling_ edge.
+The processor-wide reset can be triggered at any of the following sources:
+
+* the asynchronous, low-active `rstn_i` top entity signal
+* the <<_on_chip_debugger_ocd>>
+* the <<_watchdog_timer_wdt>>
+
+If any of these sources trigger a reset, the internal reset will be triggered for at least clock cycles resetting
+the CPU, the <<_processor_clocking>> system and the IO/peripheral devices. The internal reset is asserted
+_aysynchronoulsy_ if triggered by the external `rstn_i` signal. For internal sources, the global reset is asserted
+_synchronously_. If the reset cause gets inactive the internal reset is de-asserted _synchronously_ at a falling
+clock edge.
+
+Internally, all the processor registers that do provide a hardware reset use an **asynchronous reset**. Using a
+synchronous reset might increase logic utilization (and increase the critical path) for FPGAs that do not provide a
+"native" synchronous reset for their flip flops. For an ASIC implementation an asynchronous reset ensures that the
+whole logic is set to a defined state even if the clock is not yet operational.
+
+In order to reduce routing constraints (and by this the actual hardware requirements), some _uncritical registers_
+of the NEORV32 CPU as well as many registers of the whole NEORV32 Processor **do not use a dedicated hardware reset**.
+"Uncritical registers" in this context means that the initial value of the according register(s) after power-up/reset
+is not relevant for a defined CPU boot/start process and will "swing in" (get updated) by the controlling logic right
+after the reset has been de-asserted.
+
+In terms of the NEORV32 CPU, there are several pipeline registers, state machine registers and even some status
+and control registers (CSRs) that do not require a defined initial state to ensure a correct boot process. The
+pipeline register will get initialized by the CPU's internal state machines, which are initialized from the main
+control engine that actually features a defined hardware reset
+
+Many CPU-internal register do provide an asynchronous reset described in the VHDL code, but the "don't care" value
+(VHDL `'-'`) is used for initialization of uncritical registers - effectively generating a flip-flop without a
+reset input.
 
 [TIP]
 The EE Times provided a nice article about FPGA resets. The reset system of the NEORV32 is loosely based on this
 article: https://www.eetimes.com/how-do-i-reset-my-fpga/
 
-The system-wide reset will reset the CPU, the <<_processor_clocking>> system and the IO/peripheral devices.
-
-[NOTE]
-Note that the system reset will **NOT** reset _all_ PCU register by default. See section <<_cpu_hardware_reset>>
-for more information.
-
 [NOTE]
 The system reset will only reset the control registers of each implemented IO/peripheral module. This will also
 reset the according "module enable flag" to zero, which - in turn - will cause a _synchronous_ and