[top] add WDT and OCD reset outputs

stnolting · Jan 11, 2025 · e1339fb · e1339fb
1 parent 265e333
commit e1339fb
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Showing 4 changed files with 19 additions and 9 deletions.
diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc
@@ -88,6 +88,8 @@ to all inputs and output so the synthesis tool can insert an explicit IO (bounda
 5+^| **Global Control (<<_processor_clocking>> and <<_processor_reset>>)**
 | `clk_i`          |  1 |  in | none  | global clock line, all registers triggering on rising edge
 | `rstn_i`         |  1 |  in | none  | global reset, asynchronous, **low-active**
+| `rstn_ocd_o`     |  1 | out | none  | <<_watchdog_timer_wdt>> reset output, synchronous, **low-active**
+| `rstn_wdt_o`     |  1 | out | none  | <<_on_chip_debugger_ocd>> reset output, synchronous, **low-active**
 5+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
 | `jtag_tck_i`     |  1 |  in | `'L'` | serial clock
 | `jtag_tdi_i`     |  1 |  in | `'L'` | serial data input

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100905"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100906"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -845,6 +845,8 @@ package neorv32_package is
       -- Global control --
       clk_i          : in  std_ulogic;
       rstn_i         : in  std_ulogic;
+      rstn_ocd_o     : out std_ulogic;
+      rstn_wdt_o     : out std_ulogic;
       -- JTAG on-chip debugger interface (available if OCD_EN = true) --
       jtag_tck_i     : in  std_ulogic := 'L';
       jtag_tdi_i     : in  std_ulogic := 'L';

diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd
@@ -154,6 +154,8 @@ entity neorv32_top is
     -- Global control --
     clk_i          : in  std_ulogic;                                        -- global clock, rising edge
     rstn_i         : in  std_ulogic;                                        -- global reset, low-active, async
+    rstn_ocd_o     : out std_ulogic;                                        -- watchdog reset output, low-active, sync
+    rstn_wdt_o     : out std_ulogic;                                        -- on-chip debugger reset output, low-active, sync
 
     -- JTAG on-chip debugger interface (available if OCD_EN = true) --
     jtag_tck_i     : in  std_ulogic := 'L';                                 -- serial clock
@@ -435,19 +437,21 @@ begin
   -- Clock and Reset Generators
   -- **************************************************************************************************************************
 
-  generators:
+  soc_generators:
   if true generate
 
     -- Reset Sequencer ------------------------------------------------------------------------
     -- -------------------------------------------------------------------------------------------
     neorv32_sys_reset_inst: entity neorv32.neorv32_sys_reset
     port map (
-      clk_i      => clk_i,
-      rstn_ext_i => rstn_i,
-      rstn_wdt_i => rstn_wdt,
-      rstn_dbg_i => dci_ndmrstn,
-      rstn_ext_o => rstn_ext,
-      rstn_sys_o => rstn_sys
+      clk_i       => clk_i,
+      rstn_ext_i  => rstn_i,
+      rstn_wdt_i  => rstn_wdt,
+      rstn_dbg_i  => dci_ndmrstn,
+      rstn_ext_o  => rstn_ext,
+      rstn_sys_o  => rstn_sys,
+      xrstn_wdt_o => rstn_wdt_o,
+      xrstn_ocd_o => rstn_ocd_o
     );
 
 
@@ -469,7 +473,7 @@ begin
                    clk_gen_en(CG_TWI)    & clk_gen_en(CG_TWD)   & clk_gen_en(CG_PWM)   & clk_gen_en(CG_WDT) &
                    clk_gen_en(CG_NEOLED) & clk_gen_en(CG_GPTMR) & clk_gen_en(CG_XIP)   & clk_gen_en(CG_ONEWIRE);
 
-  end generate; -- /generators
+  end generate; -- /soc_generators
 
 
   -- **************************************************************************************************************************

diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd
@@ -232,6 +232,8 @@ begin
     -- Global control --
     clk_i          => clk_gen,
     rstn_i         => rst_gen,
+    rstn_ocd_o     => open,
+    rstn_wdt_o     => open,
     -- JTAG on-chip debugger interface --
     jtag_tck_i     => '0',
     jtag_tdi_i     => '0',