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[rtl] minor timing and area optimizations (#990)
2 parents 780b8b5 + 1128a94 commit 9b47b98

10 files changed

+200
-287
lines changed

‎CHANGELOG.md

+1
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
2929

3030
| Date | Version | Comment | Ticket |
3131
|:----:|:-------:|:--------|:------:|
32+
| 16.08.2024 | 1.10.2.7 | minor CPU area and critical path optimizations; minor code cleanups | [#990](https://github.com/stnolting/neorv32/pull/990) |
3233
| 09.08.2024 | 1.10.2.6 | :warning: re-organize RTL files; all core files are now located in `rtl/core`; remove `mem` sub-folder | [#985](https://github.com/stnolting/neorv32/pull/985) |
3334
| 09.08.2024 | 1.10.2.5 | minor HDL edits | [#984](https://github.com/stnolting/neorv32/pull/984) |
3435
| 06.08.2024 | 1.10.2.4 | :warning: **Vivado IP module**: constrain minimal ALL input/output size to 1; add explicit PWM controller enable option | [#980](https://github.com/stnolting/neorv32/pull/980) |

‎rtl/core/neorv32_cpu_control.vhd

+11-12
Original file line numberDiff line numberDiff line change
@@ -103,8 +103,8 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
103103

104104
-- HPM counter auto-configuration --
105105
constant hpm_num_c : natural := cond_sel_natural_f(CPU_EXTENSION_RISCV_Zihpm, HPM_NUM_CNTS, 0);
106-
constant hpm_cnt_lo_width_c : natural := cond_sel_natural_f(boolean(HPM_CNT_WIDTH < 32), HPM_CNT_WIDTH, 32); -- width low word
107-
constant hpm_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH > 32), HPM_CNT_WIDTH-32, 0)); -- width high word
106+
constant hpm_cnt_lo_width_c : natural := min_natural_f(HPM_CNT_WIDTH, 32); -- size low word
107+
constant hpm_cnt_hi_width_c : natural := (HPM_CNT_WIDTH / 32) * (HPM_CNT_WIDTH rem 32); -- size high word
108108

109109
-- instruction fetch engine --
110110
type fetch_engine_state_t is (IF_RESTART, IF_REQUEST, IF_PENDING);
@@ -516,7 +516,6 @@ begin
516516
if (rstn_i = '0') then
517517
imm_o <= (others => '0');
518518
elsif rising_edge(clk_i) then
519-
imm_o <= (others => '0');
520519
case decode_aux.opcode is
521520
when opcode_store_c => -- S-immediate
522521
imm_o <= replicate_f(execute_engine.ir(31), 21) & execute_engine.ir(30 downto 25) & execute_engine.ir(11 downto 7);
@@ -580,6 +579,8 @@ begin
580579
-- link PC: return address --
581580
if (execute_engine.state = BRANCH) then
582581
execute_engine.link_pc <= execute_engine.next_pc(XLEN-1 downto 1) & '0';
582+
else -- output zero if not a branch instruction
583+
execute_engine.link_pc <= (others => '0');
583584
end if;
584585

585586
-- next PC: address of next instruction --
@@ -627,11 +628,11 @@ begin
627628

628629
-- PC increment for next LINEAR instruction (+2 for compressed instr., +4 otherwise) --
629630
execute_engine.next_pc_inc(XLEN-1 downto 4) <= (others => '0');
630-
execute_engine.next_pc_inc(3 downto 0) <= x"4" when ((execute_engine.is_ci = '0') or (not CPU_EXTENSION_RISCV_C)) else x"2";
631+
execute_engine.next_pc_inc(3 downto 0) <= x"2" when (execute_engine.is_ci = '1') and CPU_EXTENSION_RISCV_C else x"4";
631632

632633
-- PC output --
633634
curr_pc_o <= execute_engine.pc(XLEN-1 downto 1) & '0'; -- current PC
634-
link_pc_o <= (execute_engine.link_pc(XLEN-1 downto 1) & '0') when (execute_engine.state = BRANCHED) else (others => '0'); -- return address
635+
link_pc_o <= (execute_engine.link_pc(XLEN-1 downto 1) & '0'); -- jump-and-link return address
635636

636637

637638
-- Decoding Helper Logic ------------------------------------------------------------------
@@ -974,8 +975,7 @@ begin
974975

975976
when others => -- SYSTEM - system environment operation; no effect if illegal instruction
976977
-- ------------------------------------------------------------
977-
if (execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) and -- ENVIRONMENT
978-
(trap_ctrl.exc_buf(exc_illegal_c) = '0') then -- not an illegal instruction
978+
if (execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) and (trap_ctrl.exc_buf(exc_illegal_c) = '0') then -- non-illegal ENVIRONMENT
979979
-- three LSBs are sufficient to distinguish environment instructions --
980980
if (execute_engine.ir(instr_funct12_lsb_c+2 downto instr_funct12_lsb_c) = "000") then
981981
trap_ctrl.ecall <= '1'; -- ecall
@@ -1152,8 +1152,8 @@ begin
11521152
CPU_EXTENSION_RISCV_Sdext and (debug_ctrl.running = '0') then -- debug-mode implemented and not running?
11531153
csr_valid(0) <= '0'; -- invalid access
11541154
elsif (csr.addr(11 downto 8) = csr_cycle_c(11 downto 8)) and -- user-mode counter access
1155-
(CPU_EXTENSION_RISCV_Zicntr or CPU_EXTENSION_RISCV_Zihpm) and -- any counters available?
1156-
CPU_EXTENSION_RISCV_U and (csr.privilege_eff = '0') and (csr.mcounteren = '0') then -- user mode enabled, active and access not allowed?
1155+
(CPU_EXTENSION_RISCV_Zicntr or CPU_EXTENSION_RISCV_Zihpm) and CPU_EXTENSION_RISCV_U and -- any user-mode counters available?
1156+
(csr.privilege_eff = '0') and (csr.mcounteren = '0') then -- in user mode and access not allowed?
11571157
csr_valid(0) <= '0'; -- invalid access
11581158
elsif (csr.addr(9 downto 8) /= "00") and (csr.privilege_eff = '0') then -- invalid privilege level
11591159
csr_valid(0) <= '0'; -- invalid access
@@ -2054,11 +2054,10 @@ begin
20542054
csr.re <= '0';
20552055
csr.rdata <= (others => '0');
20562056
elsif rising_edge(clk_i) then
2057-
csr.re <= csr.re_nxt;
2057+
csr.re <= csr.re_nxt;
2058+
csr.rdata <= (others => '0'); -- output zero if no valid CSR read access operation
20582059
if (csr.re = '1') then
20592060
csr.rdata <= csr_rdata or xcsr_rdata;
2060-
else
2061-
csr.rdata <= (others => '0'); -- output zero if no valid CSR read access operation
20622061
end if;
20632062
end if;
20642063
end process csr_read_reg;

‎rtl/core/neorv32_cpu_cp_cond.vhd

+2-1
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ end neorv32_cpu_cp_cond;
3333

3434
architecture neorv32_cpu_cp_cond_rtl of neorv32_cpu_cp_cond is
3535

36+
constant zero_c : std_ulogic_vector(XLEN-1 downto 0) := (others => '0');
3637
signal rs2_zero, condition : std_ulogic;
3738

3839
begin
@@ -53,7 +54,7 @@ begin
5354
end process cond_out;
5455

5556
-- condition check --
56-
rs2_zero <= '1' when (or_reduce_f(rs2_i) = '0') else '0';
57+
rs2_zero <= '1' when (rs2_i = zero_c) else '0';
5758
condition <= rs2_zero xnor ctrl_i.ir_funct3(1); -- equal zero / non equal zero
5859

5960
-- processing done --

‎rtl/core/neorv32_cpu_cp_muldiv.vhd

+36-35
Original file line numberDiff line numberDiff line change
@@ -60,14 +60,14 @@ architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
6060
rs1_is_signed : std_ulogic;
6161
rs2_is_signed : std_ulogic;
6262
out_en : std_ulogic;
63-
rs2_abs : std_ulogic_vector(XLEN-1 downto 0);
6463
end record;
6564
signal ctrl : ctrl_t;
6665

6766
-- divider core --
6867
type div_t is record
6968
start : std_ulogic; -- start new division
7069
sign_mod : std_ulogic; -- result sign correction
70+
rs2_abs : std_ulogic_vector(XLEN-1 downto 0);
7171
remainder : std_ulogic_vector(XLEN-1 downto 0);
7272
quotient : std_ulogic_vector(XLEN-1 downto 0);
7373
sub : std_ulogic_vector(XLEN downto 0); -- try subtraction (and restore if underflow)
@@ -95,58 +95,39 @@ begin
9595
control: process(rstn_i, clk_i)
9696
begin
9797
if (rstn_i = '0') then
98-
ctrl.state <= S_IDLE;
99-
ctrl.rs2_abs <= (others => '0');
100-
ctrl.cnt <= (others => '0');
101-
ctrl.out_en <= '0';
102-
div.sign_mod <= '0';
98+
ctrl.state <= S_IDLE;
99+
ctrl.cnt <= (others => '0');
100+
ctrl.out_en <= '0';
103101
elsif rising_edge(clk_i) then
104102
-- defaults --
105103
ctrl.out_en <= '0';
104+
ctrl.cnt <= std_ulogic_vector(to_unsigned(XLEN-2, index_size_f(XLEN))); -- cycle counter initialization
106105

107-
-- FSM --
106+
-- fsm --
108107
case ctrl.state is
109108

110109
when S_IDLE => -- wait for start signal
111-
ctrl.cnt <= std_ulogic_vector(to_unsigned(XLEN-2, index_size_f(XLEN))); -- iterative cycle counter
110+
-- ------------------------------------------------------------
112111
if (start_i = '1') then -- trigger new operation
113-
if DIVISION_EN then
114-
-- DIV: check relevant input signs for result sign compensation --
115-
if (ctrl_i.ir_funct3(1 downto 0) = op_div_c(1 downto 0)) then -- signed div operation
116-
div.sign_mod <= (rs1_i(rs1_i'left) xor rs2_i(rs2_i'left)) and or_reduce_f(rs2_i); -- different signs AND divisor not zero
117-
elsif (ctrl_i.ir_funct3(1 downto 0) = op_rem_c(1 downto 0)) then -- signed rem operation
118-
div.sign_mod <= rs1_i(rs1_i'left);
119-
else
120-
div.sign_mod <= '0';
121-
end if;
122-
-- DIV: abs(rs2) --
123-
if ((rs2_i(rs2_i'left) and ctrl.rs2_is_signed) = '1') then -- signed division?
124-
ctrl.rs2_abs <= std_ulogic_vector(0 - unsigned(rs2_i)); -- make positive
125-
else
126-
ctrl.rs2_abs <= rs2_i;
127-
end if;
128-
end if;
129-
-- is fast multiplication? --
130-
if (ctrl_i.ir_funct3(2) = '0') and FAST_MUL_EN then
112+
if (ctrl_i.ir_funct3(2) = '0') and FAST_MUL_EN then -- is fast multiplication?
131113
ctrl.state <= S_DONE;
132114
else -- serial division or serial multiplication
133115
ctrl.state <= S_BUSY;
134116
end if;
135117
end if;
136118

137119
when S_BUSY => -- processing
120+
-- ------------------------------------------------------------
138121
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 1);
139122
if (or_reduce_f(ctrl.cnt) = '0') or (ctrl_i.cpu_trap = '1') then -- abort on trap
140123
ctrl.state <= S_DONE;
141124
end if;
142125

143-
when S_DONE => -- final step / enable output for one cycle
126+
when others => -- S_DONE: final step / enable output for one cycle
127+
-- ------------------------------------------------------------
144128
ctrl.out_en <= '1';
145129
ctrl.state <= S_IDLE;
146130

147-
when others => -- undefined
148-
ctrl.state <= S_IDLE;
149-
150131
end case;
151132
end if;
152133
end process control;
@@ -160,7 +141,7 @@ begin
160141
ctrl.rs2_is_signed <= '1' when (ctrl_i.ir_funct3 = op_mulh_c) or
161142
(ctrl_i.ir_funct3 = op_div_c) or (ctrl_i.ir_funct3 = op_rem_c) else '0';
162143

163-
-- start operation (do it fast!) --
144+
-- operation trigger --
164145
mul.start <= '1' when (start_i = '1') and (ctrl_i.ir_funct3(2) = '0') else '0';
165146
div.start <= '1' when (start_i = '1') and (ctrl_i.ir_funct3(2) = '1') else '0';
166147

@@ -214,14 +195,14 @@ begin
214195
if (mul.start = '1') then -- start new multiplication
215196
mul.prod(63 downto 32) <= (others => '0');
216197
mul.prod(31 downto 0) <= rs1_i;
217-
elsif (ctrl.state = S_BUSY) or (ctrl.state = S_DONE) then -- processing step or sign-finalization step
198+
elsif (ctrl.state /= S_IDLE) then -- processing steps or sign-finalization step
218199
mul.prod(63 downto 31) <= mul.add(32 downto 0);
219200
mul.prod(30 downto 0) <= mul.prod(31 downto 1);
220201
end if;
221202
end if;
222203
end process multiplier_core;
223204

224-
-- multiply with 0/1 via addition --
205+
-- multiply with 0/-1/+1 via shift and subtraction/addition --
225206
mul_update: process(mul, ctrl, rs2_i)
226207
begin
227208
if (mul.prod(0) = '1') then -- multiply with 1
@@ -258,14 +239,32 @@ begin
258239
begin
259240
if (rstn_i = '0') then
260241
div.quotient <= (others => '0');
242+
div.rs2_abs <= (others => '0');
243+
div.sign_mod <= '0';
261244
div.remainder <= (others => '0');
262245
elsif rising_edge(clk_i) then
263246
if (div.start = '1') then -- start new division
247+
-- abs(rs1) --
264248
if ((rs1_i(rs1_i'left) and ctrl.rs1_is_signed) = '1') then -- signed division?
265249
div.quotient <= std_ulogic_vector(0 - unsigned(rs1_i)); -- make positive
266250
else
267251
div.quotient <= rs1_i;
268252
end if;
253+
-- abs(rs2) --
254+
if ((rs2_i(rs2_i'left) and ctrl.rs2_is_signed) = '1') then -- signed division?
255+
div.rs2_abs <= std_ulogic_vector(0 - unsigned(rs2_i)); -- make positive
256+
else
257+
div.rs2_abs <= rs2_i;
258+
end if;
259+
-- check relevant input signs for result sign compensation --
260+
if (ctrl_i.ir_funct3(1 downto 0) = op_div_c(1 downto 0)) then -- signed div operation
261+
div.sign_mod <= (rs1_i(rs1_i'left) xor rs2_i(rs2_i'left)) and or_reduce_f(rs2_i); -- different signs AND divisor not zero
262+
elsif (ctrl_i.ir_funct3(1 downto 0) = op_rem_c(1 downto 0)) then -- signed rem operation
263+
div.sign_mod <= rs1_i(rs1_i'left);
264+
else
265+
div.sign_mod <= '0';
266+
end if;
267+
--
269268
div.remainder <= (others => '0');
270269
elsif (ctrl.state = S_BUSY) or (ctrl.state = S_DONE) then -- running?
271270
div.quotient <= div.quotient(30 downto 0) & (not div.sub(32));
@@ -279,10 +278,10 @@ begin
279278
end process divider_core;
280279

281280
-- try another subtraction (and shift) --
282-
div.sub <= std_ulogic_vector(unsigned('0' & div.remainder(30 downto 0) & div.quotient(31)) - unsigned('0' & ctrl.rs2_abs));
281+
div.sub <= std_ulogic_vector(unsigned('0' & div.remainder(30 downto 0) & div.quotient(31)) - unsigned('0' & div.rs2_abs));
283282

284283
-- result and sign compensation --
285-
div.res_u <= div.quotient when (ctrl_i.ir_funct3 = op_div_c) or (ctrl_i.ir_funct3 = op_divu_c) else div.remainder;
284+
div.res_u <= div.quotient when (ctrl_i.ir_funct3(2 downto 1) = op_div_c(2 downto 1)) else div.remainder; -- division only
286285
div.res <= std_ulogic_vector(0 - unsigned(div.res_u)) when (div.sign_mod = '1') else div.res_u;
287286

288287
end generate; -- /divider_core_serial
@@ -291,6 +290,8 @@ begin
291290
divider_core_serial_none:
292291
if not DIVISION_EN generate
293292
div.quotient <= (others => '0');
293+
div.sign_mod <= '0';
294+
div.rs2_abs <= (others => '0');
294295
div.remainder <= (others => '0');
295296
div.sub <= (others => '0');
296297
div.res_u <= (others => '0');

‎rtl/core/neorv32_cpu_cp_shifter.vhd

+9-12
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
-- ================================================================================ --
22
-- NEORV32 CPU - Co-Processor: Shifter (CPU Base ISA) --
33
-- -------------------------------------------------------------------------------- --
4-
-- # FAST_SHIFT_EN = false -> Use bit-serial shifter architecture (small but slow) --
5-
-- # FAST_SHIFT_EN = true -> Use barrel shifter architecture (large but fast) --
4+
-- FAST_SHIFT_EN = false -> Use bit-serial shifter architecture (small but slow) --
5+
-- FAST_SHIFT_EN = true -> Use barrel shifter architecture (large but fast) --
66
-- -------------------------------------------------------------------------------- --
77
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
88
-- Copyright (c) NEORV32 contributors. --
@@ -54,7 +54,6 @@ architecture neorv32_cpu_cp_shifter_rtl of neorv32_cpu_cp_shifter is
5454
type bs_level_t is array (index_size_f(XLEN) downto 0) of std_ulogic_vector(XLEN-1 downto 0);
5555
signal bs_level : bs_level_t;
5656
signal bs_sign : std_ulogic;
57-
signal bs_start : std_ulogic;
5857
signal bs_result : std_ulogic_vector(XLEN-1 downto 0);
5958

6059
begin
@@ -108,9 +107,9 @@ begin
108107
barrel_shifter:
109108
if FAST_SHIFT_EN generate
110109

111-
-- input layer: convert left shifts to right shifts by bit-reversal --
112-
bs_level(0) <= bit_rev_f(rs1_i) when (ctrl_i.ir_funct3(2) = '0') else rs1_i;
113-
bs_sign <= rs1_i(XLEN-1) and ctrl_i.ir_funct12(10); -- sign extension for arithmetic shifts
110+
-- input layer: operand gating and convert left shifts to right shifts by bit-reversal --
111+
bs_level(0) <= (others => '0') when (start_i = '0') else bit_rev_f(rs1_i) when (ctrl_i.ir_funct3(2) = '0') else rs1_i;
112+
bs_sign <= rs1_i(XLEN-1) and ctrl_i.ir_funct12(10) and start_i; -- sign extension for arithmetic shifts
114113

115114
-- mux layers: right-shifts only --
116115
barrel_shifter_core:
@@ -119,20 +118,18 @@ begin
119118
bs_level(i+1)((XLEN-(2**i))-1 downto 0) <= bs_level(i)(XLEN-1 downto 2**i) when (shamt_i(i) = '1') else bs_level(i)((XLEN-(2**i))-1 downto 0);
120119
end generate;
121120

122-
-- pipeline register --
121+
-- register layer (can be moved by the register balancing) --
123122
barrel_shifter_buf: process(rstn_i, clk_i)
124123
begin
125124
if (rstn_i = '0') then
126-
bs_start <= '0';
127125
bs_result <= (others => '0');
128-
elsif rising_edge(clk_i) then -- this register stage can be moved by the register balancing
129-
bs_start <= start_i;
126+
elsif rising_edge(clk_i) then
130127
bs_result <= bs_level(index_size_f(XLEN));
131128
end if;
132129
end process barrel_shifter_buf;
133130

134-
-- output layer: output gate and re-convert original left shifts --
135-
res_o <= (others => '0') when (bs_start = '0') else bit_rev_f(bs_result) when (ctrl_i.ir_funct3(2) = '0') else bs_result;
131+
-- output layer: re-convert original left shifts --
132+
res_o <= bit_rev_f(bs_result) when (ctrl_i.ir_funct3(2) = '0') else bs_result;
136133
valid_o <= start_i;
137134

138135
end generate;

‎rtl/core/neorv32_cpu_pmp.vhd

+9-9
Original file line numberDiff line numberDiff line change
@@ -328,23 +328,23 @@ begin
328328
perm_gen: process(csr.cfg, ctrl_i)
329329
begin
330330
-- execute (X) --
331-
if (ctrl_i.cpu_priv = priv_mode_m_c) then -- M mode: always allow if lock bit
332-
region.perm_ex(r) <= csr.cfg(r)(cfg_x_c) or (not csr.cfg(r)(cfg_l_c));
333-
else -- U mode: check actual permission
331+
if (ctrl_i.cpu_priv = priv_mode_m_c) then
332+
region.perm_ex(r) <= csr.cfg(r)(cfg_x_c) or (not csr.cfg(r)(cfg_l_c)); -- M mode: always allow if not locked
333+
else
334334
region.perm_ex(r) <= csr.cfg(r)(cfg_x_c);
335335
end if;
336336
-- read (R) --
337337
if (ctrl_i.lsu_rw = '0') then
338-
if (ctrl_i.lsu_priv = priv_mode_m_c) then -- M mode: always allow if lock bit
339-
region.perm_rw(r) <= csr.cfg(r)(cfg_r_c) or (not csr.cfg(r)(cfg_l_c));
340-
else -- U mode: check actual permission
338+
if (ctrl_i.lsu_priv = priv_mode_m_c) then
339+
region.perm_rw(r) <= csr.cfg(r)(cfg_r_c) or (not csr.cfg(r)(cfg_l_c)); -- M mode: always allow if not locked
340+
else
341341
region.perm_rw(r) <= csr.cfg(r)(cfg_r_c);
342342
end if;
343343
-- write (W) --
344344
else
345-
if (ctrl_i.lsu_priv = priv_mode_m_c) then -- M mode: always allow if lock bit
346-
region.perm_rw(r) <= csr.cfg(r)(cfg_w_c) or (not csr.cfg(r)(cfg_l_c));
347-
else -- U mode: check actual permission
345+
if (ctrl_i.lsu_priv = priv_mode_m_c) then
346+
region.perm_rw(r) <= csr.cfg(r)(cfg_w_c) or (not csr.cfg(r)(cfg_l_c)); -- M mode: always allow if not locked
347+
else
348348
region.perm_rw(r) <= csr.cfg(r)(cfg_w_c);
349349
end if;
350350
end if;

‎rtl/core/neorv32_cpu_regfile.vhd

+6-3
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ begin
104104
register_file: process(rstn_i, clk_i)
105105
begin
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if (rstn_i = '0') then
107-
reg_file(i) <= (others => '0');
107+
reg_file(i) <= (others => '0'); -- full hardware reset
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elsif rising_edge(clk_i) then
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if (unsigned(ctrl_i.rf_rd(addr_bits_c-1 downto 0)) = to_unsigned(i, addr_bits_c)) and (ctrl_i.rf_wb_en = '1') then
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reg_file(i) <= rd_i;
@@ -117,9 +117,12 @@ begin
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reg_file(0) <= (others => '0');
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-- synchronous read --
120-
rf_read: process(clk_i)
120+
rf_read: process(rstn_i, clk_i)
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begin
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if rising_edge(clk_i) then
122+
if (rstn_i = '0') then
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rs1_o <= (others => '0');
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rs2_o <= (others => '0');
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elsif rising_edge(clk_i) then
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rs1_o <= reg_file(to_integer(unsigned(ctrl_i.rf_rs1(addr_bits_c-1 downto 0))));
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rs2_o <= reg_file(to_integer(unsigned(ctrl_i.rf_rs2(addr_bits_c-1 downto 0))));
125128
end if;

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