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✨ add support for RISC-V Zks* ISA extensions (#1040)
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‎CHANGELOG.md

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@@ -29,10 +29,11 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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| Date | Version | Comment | Ticket |
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|:----:|:-------:|:--------|:------:|
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| 28.09.2024 | 1.10.4.9 | :sparkles: add support for RISC-V "ShangMi algorithm suite" ISA extensions: `Zks`, `Zksed`, `Zksh` | [#1040](https://github.com/stnolting/neorv32/pull/1040) |
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| 28.09.2024 | 1.10.4.8 | :sparkles: add support for RISC-V "NIST algorithm suite" ISA extension `Zkn` | [#1039](https://github.com/stnolting/neorv32/pull/1039) |
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| 27.09.2024 | 1.10.4.7 | :sparkles: add support for RISC-V "carry-less multiplication instruction for cryptography" ISA extension `Zbkc` | [#1038](https://github.com/stnolting/neorv32/pull/1038) |
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| 27.09.2024 | 1.10.4.6 | :sparkles: add support for RISC-V "bit manipulation instructions for cryptography" ISA extension `Zbkb` | [#1037](https://github.com/stnolting/neorv32/pull/1037) |
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| 27.09.2024 | 1.10.4.5 | :sparkles: add support for RISC-V "data independent execution time" ISA extension `Zknt` | [#1036](https://github.com/stnolting/neorv32/pull/1036) |
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| 27.09.2024 | 1.10.4.5 | :sparkles: add support for RISC-V "data independent execution time" ISA extension `Zkt` | [#1036](https://github.com/stnolting/neorv32/pull/1036) |
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| 25.09.2024 | 1.10.4.4 | :sparkles: add support for RISC-V "scalar cryptography" ISA extensions `Zbkx`, `Zknd`, `Zkne`, `Zknh` | [#1033](https://github.com/stnolting/neorv32/pull/1033) |
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| 23.09.2024 | 1.10.4.3 | rework/optimize ALU instruction decoding and CPU co-processor interface | [#1032](https://github.com/stnolting/neorv32/pull/1032) |
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| 20.09.2024 | 1.10.4.2 | :bug: fix minor bug in FPU's multiplication instruction (invalid-check logic if any operand is sNAN) | [#1028](https://github.com/stnolting/neorv32/pull/1028) |

‎README.md

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@@ -118,10 +118,14 @@ setup according to your needs. Note that all of the following SoC modules are en
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_isa_extension)]
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[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_isa_extension)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_isa_extension)]
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[[`Zkn`](https://stnolting.github.io/neorv32/#_zkn_isa_extension)]
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[[`Zknd`](https://stnolting.github.io/neorv32/#_zknd_isa_extension)]
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[[`Zkne`](https://stnolting.github.io/neorv32/#_zkne_isa_extension)]
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[[`Zknh`](https://stnolting.github.io/neorv32/#_zknh_isa_extension)]
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[[`Zknt`](https://stnolting.github.io/neorv32/#_zknt_isa_extension)]
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[[`Zkt`](https://stnolting.github.io/neorv32/#_zkt_isa_extension)]
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[[`Zks`](https://stnolting.github.io/neorv32/#_zks_isa_extension)]
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[[`Zksed`](https://stnolting.github.io/neorv32/#_zksed_isa_extension)]
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[[`Zksh`](https://stnolting.github.io/neorv32/#_zksh_isa_extension)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_isa_extension)]
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[[`Zxcfu`](https://stnolting.github.io/neorv32/#_zxcfu_isa_extension)]
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[[`Sdext`](https://stnolting.github.io/neorv32/#_sdext_isa_extension)]

‎docs/datasheet/cpu.adoc

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@@ -432,33 +432,36 @@ This chapter gives a brief overview of all available ISA extensions.
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[options="header",grid="rows"]
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|=======================
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| Name | Description | <<_processor_top_entity_generics, Enabled by Generic>>
435-
| <<_a_isa_extension,`A`>> | Atomic memory access instructions | `CPU_EXTENSION_RISCV_A`
436-
| <<_b_isa_extension,`B`>> | Bit-manipulation instructions | `CPU_EXTENSION_RISCV_B`
437-
| <<_c_isa_extension,`C`>> | Compressed (16-bit) instructions | `CPU_EXTENSION_RISCV_C`
438-
| <<_e_isa_extension,`E`>> | Embedded CPU extension (reduced register file size) | `CPU_EXTENSION_RISCV_E`
439-
| <<_i_isa_extension,`I`>> | Integer base ISA | Enabled if `CPU_EXTENSION_RISCV_E` is **not** enabled
440-
| <<_m_isa_extension,`M`>> | Integer multiplication and division instructions | `CPU_EXTENSION_RISCV_M`
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| <<_u_isa_extension,`U`>> | Less-privileged _user_ mode extension | `CPU_EXTENSION_RISCV_U`
442-
| <<_x_isa_extension,`X`>> | Platform-specific / NEORV32-specific extension | Always enabled
443-
| <<_zbkb_isa_extension,`Zbkb`>> | Scalar cryptographic bit manipulation instructions | `CPU_EXTENSION_RISCV_Zbkb`
444-
| <<_zbkc_isa_extension,`Zbkc`>> | Scalar cryptographic carry-less multiplication instructions | `CPU_EXTENSION_RISCV_Zbkc`
445-
| <<_zbkx_isa_extension,`Zbkx`>> | Scalar cryptographic crossbar permutation instructions | `CPU_EXTENSION_RISCV_Zbkx`
446-
| <<_zfinx_isa_extension,`Zfinx`>> | Floating-point instructions using integer registers | `CPU_EXTENSION_RISCV_Zfinx`
447-
| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction | Always enabled
448-
| <<_zicntr_isa_extension,`Zicntr`>> | Base counters extension | `CPU_EXTENSION_RISCV_Zicntr`
449-
| <<_zicond_isa_extension,`Zicond`>> | Integer conditional operations | `CPU_EXTENSION_RISCV_Zicond`
450-
| <<_zicsr_isa_extension,`Zicsr`>> | Control and status register access instructions | Always enabled
451-
| <<_zihpm_isa_extension,`Zihpm`>> | Hardware performance monitors extension | `CPU_EXTENSION_RISCV_Zihpm`
452-
| <<_zkn_isa_extension,`Zkn`>> | Scalar cryptographic NIST algorithm suite | _Implicitly_ enabled
453-
| <<_zknd_isa_extension,`Zknd`>> | Scalar cryptographic NIST AES decryption instructions | `CPU_EXTENSION_RISCV_Zknd`
454-
| <<_zkne_isa_extension,`Zkne`>> | Scalar cryptographic NIST AES encryption instructions | `CPU_EXTENSION_RISCV_Zkne`
455-
| <<_zknh_isa_extension,`Zknh`>> | Scalar cryptographic NIST hash function instructions | `CPU_EXTENSION_RISCV_Zknh`
456-
| <<_zknt_isa_extension,`Zknt`>> | Data independent execution time (of cryptographic operations) | _Implicitly_ enabled
457-
| <<_zmmul_isa_extension,`Zmmul`>> | Integer multiplication-only instructions | `CPU_EXTENSION_RISCV_Zmmul`
458-
| <<_zxcfu_isa_extension,`Zcfu`>> | Custom / user-defined instructions | `CPU_EXTENSION_RISCV_Zxcfu`
459-
| <<_smpmp_isa_extension,`Smpmp`>> | Physical memory protection (PMP) extension | `CPU_EXTENSION_RISCV_Smpmp`
460-
| <<_sdext_isa_extension,`Sdext`>> | External debug support extension | `ON_CHIP_DEBUGGER_EN`
461-
| <<_sdtrig_isa_extension,`Sdtrig`>> | Trigger module extension | `ON_CHIP_DEBUGGER_EN`
435+
| <<_a_isa_extension,`A`>> | Atomic memory access instructions | `CPU_EXTENSION_RISCV_A`
436+
| <<_b_isa_extension,`B`>> | Bit-manipulation instructions | `CPU_EXTENSION_RISCV_B`
437+
| <<_c_isa_extension,`C`>> | Compressed (16-bit) instructions | `CPU_EXTENSION_RISCV_C`
438+
| <<_e_isa_extension,`E`>> | Embedded CPU extension (reduced register file size) | `CPU_EXTENSION_RISCV_E`
439+
| <<_i_isa_extension,`I`>> | Integer base ISA | Enabled if `CPU_EXTENSION_RISCV_E` is **not** enabled
440+
| <<_m_isa_extension,`M`>> | Integer multiplication and division instructions | `CPU_EXTENSION_RISCV_M`
441+
| <<_u_isa_extension,`U`>> | Less-privileged _user_ mode extension | `CPU_EXTENSION_RISCV_U`
442+
| <<_x_isa_extension,`X`>> | Platform-specific / NEORV32-specific extension | Always enabled
443+
| <<_zbkb_isa_extension,`Zbkb`>> | Scalar cryptographic bit manipulation instructions | `CPU_EXTENSION_RISCV_Zbkb`
444+
| <<_zbkc_isa_extension,`Zbkc`>> | Scalar cryptographic carry-less multiplication instructions | `CPU_EXTENSION_RISCV_Zbkc`
445+
| <<_zbkx_isa_extension,`Zbkx`>> | Scalar cryptographic crossbar permutation instructions | `CPU_EXTENSION_RISCV_Zbkx`
446+
| <<_zfinx_isa_extension,`Zfinx`>> | Floating-point instructions using integer registers | `CPU_EXTENSION_RISCV_Zfinx`
447+
| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction | Always enabled
448+
| <<_zicntr_isa_extension,`Zicntr`>> | Base counters extension | `CPU_EXTENSION_RISCV_Zicntr`
449+
| <<_zicond_isa_extension,`Zicond`>> | Integer conditional operations | `CPU_EXTENSION_RISCV_Zicond`
450+
| <<_zicsr_isa_extension,`Zicsr`>> | Control and status register access instructions | Always enabled
451+
| <<_zihpm_isa_extension,`Zihpm`>> | Hardware performance monitors extension | `CPU_EXTENSION_RISCV_Zihpm`
452+
| <<_zkn_isa_extension,`Zkn`>> | Scalar cryptographic NIST algorithm suite | _Implicitly_ enabled
453+
| <<_zknd_isa_extension,`Zknd`>> | Scalar cryptographic NIST AES decryption instructions | `CPU_EXTENSION_RISCV_Zknd`
454+
| <<_zkne_isa_extension,`Zkne`>> | Scalar cryptographic NIST AES encryption instructions | `CPU_EXTENSION_RISCV_Zkne`
455+
| <<_zknh_isa_extension,`Zknh`>> | Scalar cryptographic NIST hash function instructions | `CPU_EXTENSION_RISCV_Zknh`
456+
| <<_zkt_isa_extension,`Zkt`>> | Data independent execution time (of cryptographic operations) | _Implicitly_ enabled
457+
| <<_zks_isa_extension,`Zks`>> | Scalar cryptographic ShangMi algorithm suite | _Implicitly_ enabled
458+
| <<_zksed_isa_extension,`Zksed`>> | Scalar cryptographic ShangMi block cypher instructions | `CPU_EXTENSION_RISCV_Zksed`
459+
| <<_zksh_isa_extension,`Zksh`>> | Scalar cryptographic ShangMi hash instructions | `CPU_EXTENSION_RISCV_Zksh`
460+
| <<_zmmul_isa_extension,`Zmmul`>> | Integer multiplication-only instructions | `CPU_EXTENSION_RISCV_Zmmul`
461+
| <<_zxcfu_isa_extension,`Zcfu`>> | Custom / user-defined instructions | `CPU_EXTENSION_RISCV_Zxcfu`
462+
| <<_smpmp_isa_extension,`Smpmp`>> | Physical memory protection (PMP) extension | `CPU_EXTENSION_RISCV_Smpmp`
463+
| <<_sdext_isa_extension,`Sdext`>> | External debug support extension | `ON_CHIP_DEBUGGER_EN`
464+
| <<_sdtrig_isa_extension,`Sdtrig`>> | Trigger module extension | `ON_CHIP_DEBUGGER_EN`
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|=======================
463466

464467
.RISC-V ISA Specification
@@ -799,24 +802,6 @@ Accessing any user-mode HPM CSR (`hpmcounter*[h]`) will raise an illegal instruc
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The event-driven increment of the HPMs can be deactivated individually via the <<_mcountinhibit>> CSR.
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802-
==== `Zbn` ISA Extension
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The `Zkn` ISA extension is part of the _RISC-V scalar cryptography_ ISA specification and defines the "NIST algorithm suite".
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This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of cryptography-related
806-
sub-extensions is enabled.
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The `Zkn` extension is shorthand for the following set of other extensions:
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* <<_zbkb_isa_extension>> - Bit manipulation instructions for cryptography.
811-
* <<_zbkc_isa_extension>> - Carry-less multiply instructions.
812-
* <<_zbkx_isa_extension>> - Cross-bar permutation instructions.
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* <<_zbne_isa_extension>> - AES encryption instructions.
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* <<_zbnd_isa_extension>> - AES decryption instructions.
815-
* <<_zbnh_isa_extension>> - SHA2 hash function instructions.
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A processor configuration which implements `Zkn` must implement all of the above extensions.
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==== `Zbkb` ISA Extension
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The `Zbkb` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and extends the _RISC-V bit manipulation_
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|=======================
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==== `Zkn` ISA Extension
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The `Zkn` ISA extension is part of the _RISC-V scalar cryptography_ ISA specification and defines the "NIST algorithm suite".
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This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of cryptography-related
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sub-extensions is enabled.
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The `Zkn` extension is shorthand for the following set of other extensions:
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* <<_zbkb_isa_extension>> - Bit manipulation instructions for cryptography.
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* <<_zbkc_isa_extension>> - Carry-less multiply instructions.
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* <<_zbkx_isa_extension>> - Cross-bar permutation instructions.
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* <<_zkne_isa_extension>> - AES encryption instructions.
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* <<_zknd_isa_extension>> - AES decryption instructions.
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* <<_zknh_isa_extension>> - SHA2 hash function instructions.
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A processor configuration which implements `Zkn` must implement all of the above extensions.
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==== `Zknd` ISA Extension
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The `Zknd` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds NIST AES decryption instructions.
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|=======================
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914-
==== `Zknt` ISA Extension
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==== `Zks` ISA Extension
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The `Zks` ISA extension is part of the _RISC-V scalar cryptography_ ISA specification and defines the "ShangMi algorithm suite".
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This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of cryptography-related
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sub-extensions is enabled.
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The `Zks` extension is shorthand for the following set of other extensions:
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* <<_zbkb_isa_extension>> - Bit manipulation instructions for cryptography.
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* <<_zbkc_isa_extension>> - Carry-less multiply instructions.
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* <<_zbkx_isa_extension>> - Cross-bar permutation instructions.
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* <<_zksed_isa_extension>> - SM4 block cipher instructions.
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* <<_zksh_isa_extension>> - SM3 hash function instructions.
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A processor configuration which implements `Zks` must implement all of the above extensions.
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==== `Zksed` ISA Extension
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The `Zksed` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds ShangMi block cypher
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and key schedule instructions. It is enabled by the top's `CPU_EXTENSION_RISCV_Zksed` generic.
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This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_crypto.vhd`).
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.Instructions and Timing
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[cols="<2,<4,<3"]
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[options="header", grid="rows"]
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|=======================
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| Class | Instructions | Execution cycles
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| Block cyphers | `sm4ed` | 6
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| Key schedule | `sm4ks` | 6
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|=======================
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==== `Zksh` ISA Extension
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The `Zksh` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds ShangMi hash function instructions.
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It is enabled by the top's `CPU_EXTENSION_RISCV_Zksh` generic.
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This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_crypto.vhd`).
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.Instructions and Timing
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[cols="<2,<4,<3"]
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[options="header", grid="rows"]
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|=======================
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| Class | Instructions | Execution cycles
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| Hash | `sm3p0` `sm3p1` | 6
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|=======================
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==== `Zkt` ISA Extension
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916-
The `Zknt` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and guarantees data independent execution
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The `Zkt` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and guarantees data independent execution
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times of cryptographic and cryptography-related instructions. The ISA extension cannot be enabled by a specific generic.
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Instead, it is enabled implicitly by certain CPU configurations.
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The RISC-V `Zknt` specifications provides a list of instructions that are included within this specification.
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The RISC-V `Zkt` specifications provides a list of instructions that are included within this specification.
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However, not all instructions are required to be implemented. Rather, every one of these instructions that the
922-
core does implement must adhere to the requirements of `Zknt`.
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core does implement must adhere to the requirements of `Zkt`.
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.`Zknt` instruction listing
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.`Zkt` instruction listing
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[cols="<1,<6,<3"]
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[options="header", grid="rows"]
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|=======================
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| `RVM` | `mul[h]` `mulh[s]u` | yes
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.2+<| `RVC` <| `c.nop` `c.addi` `c.lui` `c.andi` `c.sub` `c.xor` `c.and` `c.mv` `c.add` <| yes
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<| `c.srli` `c.srai` `c.slli` <| yes if `FAST_SHIFT_EN` enabled
934-
| `RVK` | `aes32ds[m]i` `aes32es[m]i` `sha256sig*` `sha512sig*` `sha512sum*` | yes
985+
| `RVK` | `aes32ds[m]i` `aes32es[m]i` `sha256sig*` `sha512sig*` `sha512sum*` `sm3p0` `sm3p1` `sm4ed` `sm4ks` | yes
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.2+<| `RVB` <| `xperm4` `xperm8` `andn` `orn` `xnor` `pack[h]` `brev8` `rev8` <| yes
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<| `ror[i]` `rol` <| yes if `FAST_SHIFT_EN` enabled
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|=======================

‎docs/datasheet/cpu_csr.adoc

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@@ -951,7 +951,7 @@ discover ISA sub-extensions and CPU configuration options
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| 1 | `CSR_MXISA_ZIFENCEI` | r/- | <<_zifencei_isa_extension>> available
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| 2 | `CSR_MXISA_ZMMUL` | r/- | <<_zmmul_isa_extension>> available
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| 3 | `CSR_MXISA_ZXCFU` | r/- | <<_zxcfu_isa_extension>> available
954-
| 4 | `CSR_MXISA_ZKNT` | r/- | <<_zknt_isa_extension>> available
954+
| 4 | `CSR_MXISA_ZKT` | r/- | <<_zkt_isa_extension>> available
955955
| 5 | `CSR_MXISA_ZFINX` | r/- | <<_zfinx_isa_extension>> available
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| 6 | `CSR_MXISA_ZICOND` | r/- | <<_zicond_isa_extension>> available
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| 7 | `CSR_MXISA_ZICNTR` | r/- | <<_zicntr_isa_extension>> available
@@ -966,7 +966,10 @@ discover ISA sub-extensions and CPU configuration options
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| 16 | `CSR_MXISA_ZBKB` | r/- | <<_zbkb_isa_extension>> available
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| 17 | `CSR_MXISA_ZBKC` | r/- | <<_zbkc_isa_extension>> available
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| 18 | `CSR_MXISA_ZKN` | r/- | <<_zkn_isa_extension>> available
969-
| 23:19 | - | r/- | hardwired to zero
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| 19 | `CSR_MXISA_ZKSH` | r/- | <<_zksh_isa_extension>> available
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| 20 | `CSR_MXISA_ZKSED` | r/- | <<_zksed_isa_extension>> available
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| 21 | `CSR_MXISA_ZKS` | r/- | <<_zks_isa_extension>> available
972+
| 23:22 | - | r/- | hardwired to zero
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| 24 | `CSR_MXISA_IS_SIM` | r/- | set if CPU is being **simulated** (⚠️ not guaranteed)
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| 28:25 | - | r/- | hardwired to zero
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| 29 | `CSR_MXISA_RFHWRST` | r/- | full hardware reset of register file available when set (`REGFILE_HW_RST`)

‎docs/datasheet/soc.adoc

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@@ -218,10 +218,12 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
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| `CPU_EXTENSION_RISCV_Zicntr` | boolean | true | Enable <<_zicntr_isa_extension>> (CPU base counters).
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| `CPU_EXTENSION_RISCV_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional instructions).
220220
| `CPU_EXTENSION_RISCV_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors).
221+
| `CPU_EXTENSION_RISCV_Zknd` | boolean | false | Enable <<_zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
222+
| `CPU_EXTENSION_RISCV_Zkne` | boolean | false | Enable <<_zkne_isa_extension>> (scalar cryptography NIST AES encryption instructions).
223+
| `CPU_EXTENSION_RISCV_Zknh` | boolean | false | Enable <<_zknh_isa_extension>> (scalar cryptography NIST hash instructions).
224+
| `CPU_EXTENSION_RISCV_Zksh` | boolean | false | Enable <<_zksh_isa_extension>> (scalar cryptography ShangMi hash functions).
225+
| `CPU_EXTENSION_RISCV_Zksed` | boolean | false | Enable <<_zksed_isa_extension>> (scalar cryptography ShangMi block cyphers).
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| `CPU_EXTENSION_RISCV_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
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| CPU_EXTENSION_RISCV_Zknd` | boolean | false | Enable <<_zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
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| CPU_EXTENSION_RISCV_Zkne` | boolean | false | Enable <<_zkne_isa_extension>> (scalar cryptography NIST AES encryption instructions).
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| CPU_EXTENSION_RISCV_Zknh` | boolean | false | Enable <<_zknh_isa_extension>> (scalar cryptography NIST hash instructions).
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| `CPU_EXTENSION_RISCV_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).
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4+^| **CPU <<_architecture>> Tuning Options**
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| `FAST_MUL_EN` | boolean | false | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.

‎docs/figures/neorv32_processor.png

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