Minor rtl edits/cleanups (#931)

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 23.06.2024 | 1.10.0.4 | minor rtl edits/cleanups | [#931](https://github.com/stnolting/neorv32/pull/931) |
 | 22.06.2024 | 1.10.0.3 | UARTs: add flags to clear RX/TX FIFOs; DMA: add FIRQ trigger type configuration flag | [#930](https://github.com/stnolting/neorv32/pull/930) |
 | 21.06.2024 | 1.10.0.2 | minor code rtl clean-ups; fix some missing TOP defaults | [#929](https://github.com/stnolting/neorv32/pull/929) |
 | 17.05.2024 | 1.10.0.1 | :warning: remove (optional and redundant) JTAG reset signal `jtag_trst_i` | [#928](https://github.com/stnolting/neorv32/pull/928) |

rtl/core/mem/README.md

@@ -1,14 +1,18 @@
-# Processor Memory Source Files
+## Processor Memory Source Files
 
 This folder provides the architecture-only VHDL sources for the processor-internal memories
-(instruction memory "IMEM", data memory "DMEM"). Different implementations are available - but
-only **one** version of each (IMEM and DMEM) has to be added as actual source files.
+(instruction memory "IMEM", data memory "DMEM"). Different implementations are available, but
+only **one** version of each (IMEM and DMEM) should be added as actual source files.
 
-For the first implementation the `*.default.vhd` files should be selected. The HDL style for describing
-memories used by these files has proven **platform-independence** across several FPGA architectures and toolchains.
+For an initial setup the `*.default.vhd` files should be selected. The HDL style for describing
+memories used by these files has proven quite good platform-independence across several FPGA
+architectures and toolchains.
 
-If synthesis fails to infer actual block RAM resources from these default files, try the legacy `*.legacy.vhd` files, which
-provide a different HDL style. These files are intended for legacy support of older Intel/Altera Quartus versions (13.0 and older). However,
-these files do **not** use platform-specific macros or primitives - so they might also work for other FPGAs and toolchains.
+If synthesis fails to infer block RAM resources from these default files, try the legacy
+`*.legacy.vhd` files, which provide a different HDL style. These files are also intended for
+legacy support of older Intel/Altera Quartus versions (13.0 and older). However, these files
+still do not use platform-specific macros or primitives - so they might also work for other
+FPGAs and toolchains.
 
-:warning: Make sure to add the selected files from this folder also to the `neorv32` design library.
+> [!IMPORTANT]
+> Make sure to add the selected files from this folder also to the `neorv32` design library.

rtl/core/mem/neorv32_imem.default.vhd

@@ -26,10 +26,6 @@ architecture neorv32_imem_rtl of neorv32_imem is
   signal rden  : std_ulogic;
   signal addr  : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
 
-  -- --------------------------- --
-  -- IMEM as pre-initialized ROM --
-  -- --------------------------- --
-
   -- application (image) size in bytes --
   constant imem_app_size_c : natural := (application_init_image'length)*4;
 

rtl/core/mem/neorv32_imem.legacy.vhd

@@ -26,10 +26,6 @@ architecture neorv32_imem_rtl of neorv32_imem is
   signal rden          : std_ulogic;
   signal addr, addr_ff : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
 
-  -- --------------------------- --
-  -- IMEM as pre-initialized ROM --
-  -- --------------------------- --
-
   -- application (image) size in bytes --
   constant imem_app_size_c : natural := (application_init_image'length)*4;