[top] fix JTAG reset default value

input is low-active, so the default is high

docs/datasheet/soc.adoc

@@ -81,7 +81,7 @@ Some interfaces (like the TWI and the 1-Wire bus) require tri-state drivers in t
 | `clk_i`          |  1 |  in | none  | global clock line, all registers triggering on rising edge
 | `rstn_i`         |  1 |  in | none  | global reset, asynchronous, **low-active**
 5+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
-| `jtag_trst_i`    |  1 |  in | `'L'` | TAP reset, low-active (optional)
+| `jtag_trst_i`    |  1 |  in | `'H'` | TAP reset, low-active (optional)
 | `jtag_tck_i`     |  1 |  in | `'L'` | serial clock
 | `jtag_tdi_i`     |  1 |  in | `'L'` | serial data input
 | `jtag_tdo_o`     |  1 | out |   -   | serial data output

rtl/core/neorv32_package.vhd

@@ -846,7 +846,7 @@ package neorv32_package is
       clk_i          : in  std_ulogic;
       rstn_i         : in  std_ulogic;
       -- JTAG on-chip debugger interface --
-      jtag_trst_i    : in  std_ulogic := 'L';
+      jtag_trst_i    : in  std_ulogic := 'H';
       jtag_tck_i     : in  std_ulogic := 'L';
       jtag_tdi_i     : in  std_ulogic := 'L';
       jtag_tdo_o     : out std_ulogic;

rtl/core/neorv32_top.vhd

@@ -157,7 +157,7 @@ entity neorv32_top is
     rstn_i         : in  std_ulogic; -- global reset, low-active, async
 
     -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
-    jtag_trst_i    : in  std_ulogic := 'L'; -- low-active TAP reset (optional)
+    jtag_trst_i    : in  std_ulogic := 'H'; -- low-active TAP reset (optional)
     jtag_tck_i     : in  std_ulogic := 'L'; -- serial clock
     jtag_tdi_i     : in  std_ulogic := 'L'; -- serial data input
     jtag_tdo_o     : out std_ulogic;        -- serial data output