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Minor rtl edits and cleanup; 🐛 fix multiple drivers bug (#1151)
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@stnolting
stnolting authored Jan 11, 2025
2 parents f5bdf69 + 69bc5bf commit 01e88db
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 12.01.2025 | 1.10.9.5 | minor rtl cleanups; :bug: fix minor bug (multiple drivers on ICC nets; introduced in version 1.10.9.2) | [#1151](https://github.com/stnolting/neorv32/pull/1151) |
| 11.01.2025 | 1.10.9.4 | :warning: RTE: use a single, global trap handler table that applies to _both_ cores | [#1150](https://github.com/stnolting/neorv32/pull/1150) |
| 10.01.2025 | 1.10.9.3 | split functional behavior of `fence` and `fence.i` instructions | [#1149](https://github.com/stnolting/neorv32/pull/1149) |
| 10.01.2025 | 1.10.9.2 | clean-up SMP dual-core configuration (HW and SW optimizations) | [#1146](https://github.com/stnolting/neorv32/pull/1146) |
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2 changes: 1 addition & 1 deletion docs/datasheet/cpu_csr.adoc
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Expand Up @@ -361,7 +361,7 @@ As software does not need to determine the interrupt cause the reduction in late
|=======================
| Name | Machine exception program counter
| Address | `0x341`
| Reset value | `BOOT_ADDR` (CPU boot address, see <<_cpu_top_entity_generics>>)
| Reset value | `0x00000000`
| ISA | `Zicsr`
| Description | The `mepc` CSR provides the instruction address where execution has stopped/failed when
an interrupt is triggered / an exception is raised. See section <<_traps_exceptions_and_interrupts>> for a list of all legal values.
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18 changes: 9 additions & 9 deletions rtl/core/neorv32_bus.vhd
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Expand Up @@ -827,7 +827,7 @@ begin
arbiter_nxt.state <= S_READ_WAIT;
end if;

when S_READ_WAIT => -- wait for device read-access to complete
when S_READ_WAIT => -- wait for read-access to complete
-- ------------------------------------------------------------
arbiter_nxt.rdata <= sys_rsp_i.data;
if (sys_rsp_i.ack = '1') or (sys_rsp_i.err = '1') then
Expand All @@ -838,11 +838,11 @@ begin
-- ------------------------------------------------------------
arbiter_nxt.state <= S_WRITE;

when S_WRITE => -- wait operation result to device
when S_WRITE => -- write operation result
-- ------------------------------------------------------------
arbiter_nxt.state <= S_WRITE_WAIT;

when S_WRITE_WAIT => -- wait for device write-access to complete
when S_WRITE_WAIT => -- wait for write-access to complete
-- ------------------------------------------------------------
if (sys_rsp_i.ack = '1') or (sys_rsp_i.err = '1') then
arbiter_nxt.state <= S_IDLE;
Expand Down Expand Up @@ -883,12 +883,12 @@ begin
alu_res <= (others => '0');
elsif rising_edge(clk_i) then
case arbiter.cmd(2 downto 0) is
when "000" => alu_res <= arbiter.wdata; -- AMOSWAP
when "001" => alu_res <= std_ulogic_vector(unsigned(arbiter.rdata) + unsigned(arbiter.wdata)); -- AMOADD
when "010" => alu_res <= arbiter.rdata xor arbiter.wdata; -- AMOXOR
when "011" => alu_res <= arbiter.rdata and arbiter.wdata; -- AMOAND
when "100" => alu_res <= arbiter.rdata or arbiter.wdata; -- AMOOR
when others => alu_res <= cmp_res; -- AMOMIN[U] / AMOMAX[U]
when "000" => alu_res <= arbiter.wdata; -- AMOSWAP.W
when "001" => alu_res <= std_ulogic_vector(unsigned(arbiter.rdata) + unsigned(arbiter.wdata)); -- AMOADD.W
when "010" => alu_res <= arbiter.rdata xor arbiter.wdata; -- AMOXOR.W
when "011" => alu_res <= arbiter.rdata and arbiter.wdata; -- AMOAND.W
when "100" => alu_res <= arbiter.rdata or arbiter.wdata; -- AMOOR.W
when others => alu_res <= cmp_res; -- AMOMIN[U].W / AMOMAX[U].W
end case;
end if;
end process amo_alu;
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4 changes: 2 additions & 2 deletions rtl/core/neorv32_cache.vhd
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Expand Up @@ -846,8 +846,8 @@ begin
bus_req_o.ben <= (others => '1'); -- full-word writes only
bus_req_o.src <= '0'; -- cache accesses are always data accesses
bus_req_o.priv <= '0'; -- cache accesses are always "unprivileged" accesses
bus_req_o.amo <= '0'; -- cache accesses can never be an atomic memory operation set operation
bus_req_o.amoop <= (others => '0'); -- cache accesses can never be an atomic memory operation set operation
bus_req_o.amo <= '0'; -- cache accesses can never be an atomic memory operation
bus_req_o.amoop <= (others => '0'); -- cache accesses can never be an atomic memory operation
bus_req_o.debug <= host_req_i.debug;
if (state = S_IDLE) then
bus_req_o.sleep <= host_req_i.sleep;
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97 changes: 51 additions & 46 deletions rtl/core/neorv32_cpu.vhd
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Expand Up @@ -136,52 +136,57 @@ begin

-- Configuration Info and Sanity Checks ---------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- CPU ISA configuration (in alphabetical order - not in canonical order!) --
assert false report "[NEORV32] CPU ISA: rv32" &
cond_sel_string_f(RISCV_ISA_E, "e", "i") &
cond_sel_string_f(riscv_b_c, "b", "" ) &
cond_sel_string_f(RISCV_ISA_C, "c", "" ) &
cond_sel_string_f(RISCV_ISA_M, "m", "" ) &
cond_sel_string_f(RISCV_ISA_U, "u", "" ) &
cond_sel_string_f(true, "x", "" ) & -- always enabled
cond_sel_string_f(RISCV_ISA_Zaamo, "_zaamo", "" ) &
cond_sel_string_f(RISCV_ISA_Zba, "_zba", "" ) &
cond_sel_string_f(RISCV_ISA_Zbb, "_zbb", "" ) &
cond_sel_string_f(RISCV_ISA_Zbkb, "_zbkb", "" ) &
cond_sel_string_f(RISCV_ISA_Zbkc, "_zbkc", "" ) &
cond_sel_string_f(RISCV_ISA_Zbkx, "_zbkx", "" ) &
cond_sel_string_f(RISCV_ISA_Zbs, "_zbs", "" ) &
cond_sel_string_f(RISCV_ISA_Zicntr, "_zicntr", "" ) &
cond_sel_string_f(RISCV_ISA_Zicond, "_zicond", "" ) &
cond_sel_string_f(true, "_zicsr", "" ) & -- always enabled
cond_sel_string_f(true, "_zifencei", "" ) & -- always enabled
cond_sel_string_f(RISCV_ISA_Zihpm, "_zihpm", "" ) &
cond_sel_string_f(RISCV_ISA_Zfinx, "_zfinx", "" ) &
cond_sel_string_f(riscv_zkn_c, "_zkn", "" ) &
cond_sel_string_f(RISCV_ISA_Zknd, "_zknd", "" ) &
cond_sel_string_f(RISCV_ISA_Zkne, "_zkne", "" ) &
cond_sel_string_f(RISCV_ISA_Zknh, "_zknh", "" ) &
cond_sel_string_f(riscv_zks_c, "_zks", "" ) &
cond_sel_string_f(RISCV_ISA_Zksed, "_zksed", "" ) &
cond_sel_string_f(RISCV_ISA_Zksh, "_zksh", "" ) &
cond_sel_string_f(riscv_zkt_c, "_zkt", "" ) &
cond_sel_string_f(RISCV_ISA_Zmmul, "_zmmul", "" ) &
cond_sel_string_f(RISCV_ISA_Zxcfu, "_zxcfu", "" ) &
cond_sel_string_f(RISCV_ISA_Sdext, "_sdext", "" ) &
cond_sel_string_f(RISCV_ISA_Sdtrig, "_sdtrig", "" ) &
cond_sel_string_f(RISCV_ISA_Smpmp, "_smpmp", "" )
severity note;

-- CPU tuning options --
assert false report "[NEORV32] CPU tuning options: " &
cond_sel_string_f(CPU_CLOCK_GATING_EN, "clock_gating ", "") &
cond_sel_string_f(CPU_FAST_MUL_EN, "fast_mul ", "") &
cond_sel_string_f(CPU_FAST_SHIFT_EN, "fast_shift ", "") &
cond_sel_string_f(CPU_RF_HW_RST_EN, "rf_hw_rst ", "")
severity note;

-- simulation notifier --
assert not is_simulation_c report "[NEORV32] Assuming this is a simulation." severity warning;
hello_neorv32:
if HART_ID = 0 generate -- print only for core 0

-- CPU ISA configuration (in alphabetical order - not in canonical order!) --
assert false report "[NEORV32] CPU ISA: rv32" &
cond_sel_string_f(RISCV_ISA_E, "e", "i") &
cond_sel_string_f(riscv_b_c, "b", "" ) &
cond_sel_string_f(RISCV_ISA_C, "c", "" ) &
cond_sel_string_f(RISCV_ISA_M, "m", "" ) &
cond_sel_string_f(RISCV_ISA_U, "u", "" ) &
cond_sel_string_f(true, "x", "" ) & -- always enabled
cond_sel_string_f(RISCV_ISA_Zaamo, "_zaamo", "" ) &
cond_sel_string_f(RISCV_ISA_Zba, "_zba", "" ) &
cond_sel_string_f(RISCV_ISA_Zbb, "_zbb", "" ) &
cond_sel_string_f(RISCV_ISA_Zbkb, "_zbkb", "" ) &
cond_sel_string_f(RISCV_ISA_Zbkc, "_zbkc", "" ) &
cond_sel_string_f(RISCV_ISA_Zbkx, "_zbkx", "" ) &
cond_sel_string_f(RISCV_ISA_Zbs, "_zbs", "" ) &
cond_sel_string_f(RISCV_ISA_Zicntr, "_zicntr", "" ) &
cond_sel_string_f(RISCV_ISA_Zicond, "_zicond", "" ) &
cond_sel_string_f(true, "_zicsr", "" ) & -- always enabled
cond_sel_string_f(true, "_zifencei", "" ) & -- always enabled
cond_sel_string_f(RISCV_ISA_Zihpm, "_zihpm", "" ) &
cond_sel_string_f(RISCV_ISA_Zfinx, "_zfinx", "" ) &
cond_sel_string_f(riscv_zkn_c, "_zkn", "" ) &
cond_sel_string_f(RISCV_ISA_Zknd, "_zknd", "" ) &
cond_sel_string_f(RISCV_ISA_Zkne, "_zkne", "" ) &
cond_sel_string_f(RISCV_ISA_Zknh, "_zknh", "" ) &
cond_sel_string_f(riscv_zks_c, "_zks", "" ) &
cond_sel_string_f(RISCV_ISA_Zksed, "_zksed", "" ) &
cond_sel_string_f(RISCV_ISA_Zksh, "_zksh", "" ) &
cond_sel_string_f(riscv_zkt_c, "_zkt", "" ) &
cond_sel_string_f(RISCV_ISA_Zmmul, "_zmmul", "" ) &
cond_sel_string_f(RISCV_ISA_Zxcfu, "_zxcfu", "" ) &
cond_sel_string_f(RISCV_ISA_Sdext, "_sdext", "" ) &
cond_sel_string_f(RISCV_ISA_Sdtrig, "_sdtrig", "" ) &
cond_sel_string_f(RISCV_ISA_Smpmp, "_smpmp", "" )
severity note;

-- CPU tuning options --
assert false report "[NEORV32] CPU tuning options: " &
cond_sel_string_f(CPU_CLOCK_GATING_EN, "clock_gating ", "") &
cond_sel_string_f(CPU_FAST_MUL_EN, "fast_mul ", "") &
cond_sel_string_f(CPU_FAST_SHIFT_EN, "fast_shift ", "") &
cond_sel_string_f(CPU_RF_HW_RST_EN, "rf_hw_rst ", "")
severity note;

-- simulation notifier --
assert not is_simulation_c report "[NEORV32] Assuming this is a simulation." severity warning;

end generate;


-- Clock Gating ---------------------------------------------------------------------------
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