Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Stm32 u5 update v1.0.2 #1595

Merged
merged 2 commits into from
Dec 15, 2021
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Original file line number Diff line number Diff line change
Expand Up @@ -259,6 +259,13 @@ extern "C" {
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif

#if defined(STM32U5)
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif

#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
Expand Down
4 changes: 2 additions & 2 deletions system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h
Original file line number Diff line number Diff line change
Expand Up @@ -218,8 +218,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 CH1 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */

/**
Expand Down
12 changes: 6 additions & 6 deletions system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h
Original file line number Diff line number Diff line change
Expand Up @@ -105,8 +105,8 @@ typedef struct
* @brief DAC Trigger stop mode
* @{
*/
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_LPTIM1_OUT /*!< LPTIM1 output selected as DAC trigger in stop mode */
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_LPTIM3_OUT /*!< LPTIM3 output selected as DAC trigger in stop mode */
#define DAC_TRIGGER_STOP_LPTIM1_CH1 DAC_TRIGGER_LPTIM1_CH1 /*!< LPTIM1 output selected as DAC trigger in stop mode */
#define DAC_TRIGGER_STOP_LPTIM3_CH1 DAC_TRIGGER_LPTIM3_CH1 /*!< LPTIM3 output selected as DAC trigger in stop mode */
#define DAC_TRIGGER_STOP_EXT_IT9 DAC_TRIGGER_EXT_IT9 /*!< EXTI line 9 selected as DAC trigger in stop mode */
/**
* @}
Expand All @@ -133,11 +133,11 @@ typedef struct
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
((TRIGGER) == DAC_TRIGGER_LPTIM1_CH1) || \
((TRIGGER) == DAC_TRIGGER_LPTIM3_CH1) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_OUT) || \
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_OUT) || \
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_CH1) || \
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_CH1) || \
((TRIGGER) == DAC_TRIGGER_STOP_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))

Expand Down
10 changes: 6 additions & 4 deletions system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h
Original file line number Diff line number Diff line change
Expand Up @@ -759,7 +759,8 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */
#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */
#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */
#define DMA_CHANNEL_ATTR_MASK (0xFFFFFFF0U) /* DMA channel attributes mask */
#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */
#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */
#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */
#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */
/**
Expand Down Expand Up @@ -839,9 +840,10 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
(((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((((~((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) >> 4U) & ((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) == 0U) && \
((ATTRIBUTE) != 0U))
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \
(((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \
(((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U)))
#else
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
(((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
Expand Down
17 changes: 6 additions & 11 deletions system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h
Original file line number Diff line number Diff line change
Expand Up @@ -3227,14 +3227,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
* @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor
* CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor
* @param ADCx ADC instance
* @param SingleDiff This parameter can be one of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
* @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
* @param CalibrationFactor Value between Min_Data=0x0000 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff,
Expand All @@ -3243,7 +3241,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32
if (ADCx == ADC1)
{
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, 0UL); /* CalibIndex == 0*/
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/
MODIFY_REG(ADCx->CALFACT2,
SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) \
Expand All @@ -3268,13 +3266,11 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32
* single-ended and differential modes
* Calibration of linearity is common to both
* single-ended and differential modes
* @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor
* CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor
* @param ADCx ADC instance
* @param SingleDiff This parameter can be one of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval Value between Min_Data=0x00 and Max_Data=0x7F
* @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
{
Expand All @@ -3285,9 +3281,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui
if (ADCx == ADC1)
{
uint32_t temp_CalibOffset;
SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, 0UL); /* CalibIndex == 0*/
MODIFY_REG(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF, ADC_CALFACT_CAPTURE_COEF);
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/
temp_CalibOffset = (READ_BIT(ADCx->CALFACT2, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) \
>> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
Expand Down Expand Up @@ -4563,7 +4558,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
/* Parse register for end of sequence identifier */
/* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
(ADC_CHSELR_SQ2), value "4" to length of end of sequence
indentifier (0xF)*/
identifier (0xF)*/
for (rank_index = 0UL; rank_index <= (28U - 4U); rank_index += 4U)
{
rank_shifted = (uint32_t)(0xF0UL << rank_index);
Expand Down
15 changes: 9 additions & 6 deletions system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h
Original file line number Diff line number Diff line change
Expand Up @@ -295,9 +295,12 @@ typedef struct
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
#define LL_DAC_TRIG_EXT_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */
#define LL_DAC_TRIG_EXT_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 CH1. */
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */

#define LL_DAC_TRIG_EXT_LPTIM1_OUT LL_DAC_TRIG_EXT_LPTIM1_CH1 /*!< Keep old definition for compatibility */
#define LL_DAC_TRIG_EXT_LPTIM3_OUT LL_DAC_TRIG_EXT_LPTIM3_CH1 /*!< Keep old definition for compatibility */
/**
* @}
*/
Expand Down Expand Up @@ -712,8 +715,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
* @retval None
*/
Expand Down Expand Up @@ -746,8 +749,8 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
*/
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
Expand Down
35 changes: 35 additions & 0 deletions system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h
Original file line number Diff line number Diff line change
Expand Up @@ -844,6 +844,41 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
}

/**
* @brief Enable I2C Fast Mode Plus (FMP = 1).
* @note 20mA I/O drive enable
* @rmtoll CR1 FMP LL_I2C_EnableFastModePlus
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
}

/**
* @brief Disable I2C Fast Mode Plus (FMP = 0).
* @note 20mA I/O drive disable
* @rmtoll CR1 FMP LL_I2C_DisableFastModePlus
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
}

/**
* @brief Check if the I2C Fast Mode Plus is enabled or disabled.
* @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
}

/**
* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
* @note Changing this bit is not allowed, when the START bit is set.
Expand Down
24 changes: 12 additions & 12 deletions system/Drivers/STM32U5xx_HAL_Driver/README.md
Original file line number Diff line number Diff line change
@@ -1,21 +1,19 @@
# STM32CubeU5 HAL Driver MCU Component

![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32u5xx_hal_driver.svg?color=brightgreen)

## Overview

**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.

**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
* The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
* The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
* A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
* A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
* The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
* The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
* A consistent set of middlewares components such as RTOS, FatFS, TCP-IP, Graphic ...
* A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series

Two models of publication are proposed for the STM32Cube embedded software:
* The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
* The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
* The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
* The **MCU component** : progressively from June 2021, each STM32Cube software module being part of the STM32Cube MCU Package, are delivered as an individual repo, allowing the user to select and get only the required software functions.

## Description

Expand All @@ -41,7 +39,9 @@ It is **crucial** that you use a consistent set of versions for the CMSIS Core -

HAL Driver | CMSIS Device | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
Tag v1.0.0 | Tag v1.0.0 | Tag v5.6.0_cm33 | Tag v1.0.0 (and following, if any, till next tag)
Tag v1.0.0 | Tag v1.0.0 | Tag v560_cm33 | Tag v1.0.0 (and following, if any, till next tag)
Tag v1.0.1 | Tag v1.0.1 | Tag v560_cm33 | Tag v1.0.1 (and following, if any, till next tag)
Tag v1.0.2 | Tag v1.0.2 | Tag v560_cm33 | Tag v1.0.2 (and following, if any, till next tag)


The full **STM32CubeU5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeU5).
Expand All @@ -50,4 +50,4 @@ The full **STM32CubeU5** MCU package is available [here](https://github.com/STMi

If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32u5xx_hal_driver/issues/new/choose).

For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/topic/0TO0X000000BSqSWAW/stm32-mcus).
For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
Loading