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Configure GPIOx_ASCR register for STM32L47x/STM32L48x #309

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Configure GPIOx_ASCR register for STM32L47x/STM32L48x #309

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4f74a92
Configure GPIOx_ASCR register for STM32L47x/STM32L48x
jspngh Apr 19, 2022
e74297a
Update PAC `stm32l4` to v0.15.1
jspngh Jul 10, 2022
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2 changes: 1 addition & 1 deletion Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ edition = "2018"
[dependencies]
cortex-m = "0.7"
nb = "0.1.1"
stm32l4 = "0.14.0"
stm32l4 = "0.15.1"
embedded-dma = "0.1"
bxcan = ">=0.4, <0.7"
fugit = "0.3.5"
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20 changes: 20 additions & 0 deletions src/gpio/convert.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -150,6 +150,26 @@ impl<MODE, HL, const P: char, const N: u8> Pin<MODE, HL, P, N> {
_pupdr: &mut PUPDR<P>,
) -> Pin<Analog, HL, P, N> {
self.mode::<Analog>();

#[cfg(any(
feature = "stm32l471",
feature = "stm32l475",
feature = "stm32l476",
feature = "stm32l485",
feature = "stm32l486",
))]
{
// On STM32L47x/L48x devices, before any conversion of an input channel coming from
// GPIO pads, it is necessary to configure the corresponding GPIOx_ASCR register
// in the GPIO, in addition to the I/O configuration in analog mode.
let offset = { N };
unsafe {
(*Gpio::<P>::ptr())
.ascr
.modify(|r, w| w.bits(r.bits() | (1 << offset)))
};
}

Pin::new()
}

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4 changes: 2 additions & 2 deletions src/pwm.rs
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Expand Up @@ -370,7 +370,7 @@ macro_rules! pwm_channels {

#[inline(always)]
fn get_duty(&self) -> Self::Duty {
unsafe { (*$TIMX::ptr()).$ccrX.read().$ccr().bits() }
unsafe { (*$TIMX::ptr()).$ccrX().read().$ccr().bits() }
}

#[inline(always)]
Expand All @@ -380,7 +380,7 @@ macro_rules! pwm_channels {

#[inline(always)]
fn set_duty(&mut self, duty: Self::Duty) {
unsafe { (*$TIMX::ptr()).$ccrX.write(|w| w.$ccr().bits(duty)) }
unsafe { (*$TIMX::ptr()).$ccrX().write(|w| w.$ccr().bits(duty)) }
}
}
)+
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4 changes: 2 additions & 2 deletions src/rtc.rs
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Expand Up @@ -271,7 +271,7 @@ impl Rtc {
rtc_registers::clear_alarm_a_flag(rtc);
while !rtc_registers::is_alarm_a_accessible(rtc) {}

rtc.alrmar.modify(|_, w| unsafe {
rtc.alrmar().modify(|_, w| unsafe {
w.dt()
.bits(dt)
.du()
Expand Down Expand Up @@ -307,7 +307,7 @@ impl Rtc {
rtc_registers::clear_alarm_b_flag(rtc);
while !rtc_registers::is_alarm_b_accessible(rtc) {}

rtc.alrmbr.modify(|_, w| unsafe {
rtc.alrmbr().modify(|_, w| unsafe {
w.dt()
.bits(dt)
.du()
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2 changes: 1 addition & 1 deletion src/tsc.rs
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Expand Up @@ -267,7 +267,7 @@ impl<SPIN> Tsc<SPIN> {
/// Reads the tsc group 2 count register
/// WARNING, just returns the contents of the register! No validation of the correct pin
pub fn read_unchecked(&self) -> u16 {
self.tsc.iog2cr.read().cnt().bits()
self.tsc.iog2cr().read().cnt().bits()
}

/// Is the tsc performing an aquisition
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27 changes: 0 additions & 27 deletions src/watchdog.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -27,34 +27,7 @@ impl IndependentWatchdog {

/// Debug independent watchdog stopped when core is halted
pub fn stop_on_debug(&self, dbgmcu: &DBGMCU, stop: bool) {
#[cfg(any(
feature = "stm32l431",
feature = "stm32l451",
feature = "stm32l471",
feature = "stm32l412",
feature = "stm32l422",
feature = "stm32l432",
feature = "stm32l442",
feature = "stm32l452",
feature = "stm32l462",
feature = "stm32l433",
feature = "stm32l443",
))]
dbgmcu.apb1fzr1.modify(|_, w| w.dbg_iwdg_stop().bit(stop));
#[cfg(not(any(
feature = "stm32l431",
feature = "stm32l451",
feature = "stm32l471",
feature = "stm32l412",
feature = "stm32l422",
feature = "stm32l432",
feature = "stm32l442",
feature = "stm32l452",
feature = "stm32l462",
feature = "stm32l433",
feature = "stm32l443",
)))]
dbgmcu.apb1_fzr1.modify(|_, w| w.dbg_iwdg_stop().bit(stop));
}

/// Sets the watchdog timer timout period. Max: 32768 ms
Expand Down