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Spi with 16bit framesize #258

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merged 8 commits into from
Aug 31, 2020
Merged

Spi with 16bit framesize #258

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3c975a5
separated 8 and 16b dataframe operation
unpaid-bill Aug 17, 2020
cd382bc
added conversion from 16b to 8b spi dataframe
unpaid-bill Aug 17, 2020
603d0c6
minor code cleanup
unpaid-bill Aug 17, 2020
4fb6d5a
added SpiReadWrite trait to reduce duplicate code
unpaid-bill Aug 25, 2020
4fc7d8a
cargo fmt and minor documentation additions
unpaid-bill Aug 25, 2020
41d3605
updated CHANGELOG.md
unpaid-bill Aug 30, 2020
728b2b3
document breaking change in CHANGELOG.md
unpaid-bill Aug 30, 2020
cc2b9be
renamed fast_write to spi_write
unpaid-bill Aug 31, 2020
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235 changes: 222 additions & 13 deletions src/spi.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -109,10 +109,11 @@ pins_impl!(
(MISO, SCK, MOSI), (Miso, Sck, Mosi), (_Miso, _Sck, _Mosi);
);

pub struct Spi<SPI, REMAP, PINS> {
pub struct Spi<SPI, REMAP, PINS, FRAMESIZE> {
spi: SPI,
pins: PINS,
_remap: PhantomData<REMAP>,
_framesize: PhantomData<FRAMESIZE>,
}

/// A filler type for when the SCK pin is unnecessary
Expand Down Expand Up @@ -147,7 +148,7 @@ remap!(Spi3NoRemap, SPI3, false, PB3, PB4, PB5);
#[cfg(feature = "connectivity")]
remap!(Spi3Remap, SPI3, true, PC10, PC11, PC12);

impl<REMAP, PINS> Spi<SPI1, REMAP, PINS> {
impl<REMAP, PINS> Spi<SPI1, REMAP, PINS, u8> {
/**
Constructs an SPI instance using SPI1.

Expand All @@ -170,11 +171,11 @@ impl<REMAP, PINS> Spi<SPI1, REMAP, PINS> {
PINS: Pins<REMAP, POS>,
{
mapr.modify_mapr(|_, w| w.spi1_remap().bit(REMAP::REMAP));
Spi::<SPI1, _, _>::_spi(spi, pins, mode, freq.into(), clocks, apb)
Spi::<SPI1, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
}
}

impl<REMAP, PINS> Spi<SPI2, REMAP, PINS> {
impl<REMAP, PINS> Spi<SPI2, REMAP, PINS, u8> {
/**
Constructs an SPI instance using SPI2.

Expand All @@ -195,12 +196,12 @@ impl<REMAP, PINS> Spi<SPI2, REMAP, PINS> {
REMAP: Remap<Periph = SPI2>,
PINS: Pins<REMAP, POS>,
{
Spi::<SPI2, _, _>::_spi(spi, pins, mode, freq.into(), clocks, apb)
Spi::<SPI2, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
}
}

#[cfg(any(feature = "high", feature = "connectivity"))]
impl<REMAP, PINS> Spi<SPI3, REMAP, PINS> {
impl<REMAP, PINS> Spi<SPI3, REMAP, PINS, u8> {
/**
Constructs an SPI instance using SPI3.

Expand All @@ -221,13 +222,13 @@ impl<REMAP, PINS> Spi<SPI3, REMAP, PINS> {
REMAP: Remap<Periph = SPI3>,
PINS: Pins<REMAP, POS>,
{
Spi::<SPI3, _, _>::_spi(spi, pins, mode, freq.into(), clocks, apb)
Spi::<SPI3, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
}
}

pub type SpiRegisterBlock = crate::pac::spi1::RegisterBlock;

impl<SPI, REMAP, PINS> Spi<SPI, REMAP, PINS>
impl<SPI, REMAP, PINS> Spi<SPI, REMAP, PINS, u8>
where
SPI: Deref<Target = SpiRegisterBlock> + Enable + Reset,
SPI::Bus: GetBusFreq,
Expand Down Expand Up @@ -300,6 +301,117 @@ where
spi,
pins,
_remap: PhantomData,
_framesize: PhantomData,
}
}

pub fn frame_size_16bit(self) -> Spi<SPI, REMAP, PINS, u16>{
self.spi.cr1.modify(|_, w| w.spe().clear_bit());
self.spi.cr1.modify(|_, w| w.dff().set_bit());
self.spi.cr1.modify(|_, w| w.spe().set_bit());
Spi{
spi: self.spi,
pins: self.pins,
_remap: PhantomData,
_framesize: PhantomData,
}
}

#[deprecated(since = "0.6.0", note = "Please use release instead")]
pub fn free(self) -> (SPI, PINS) {
self.release()
}
pub fn release(self) -> (SPI, PINS) {
(self.spi, self.pins)
}
}

impl<SPI, REMAP, PINS> Spi<SPI, REMAP, PINS, u16>
where
SPI: Deref<Target = SpiRegisterBlock> + Enable + Reset,
SPI::Bus: GetBusFreq,
{
fn _spi(
spi: SPI,
pins: PINS,
mode: Mode,
freq: Hertz,
clocks: Clocks,
apb: &mut SPI::Bus,
) -> Self {
// enable or reset SPI
SPI::enable(apb);
SPI::reset(apb);

// disable SS output
spi.cr2.write(|w| w.ssoe().clear_bit());

let br = match SPI::Bus::get_frequency(&clocks).0 / freq.0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=47 => 0b100,
48..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
};

spi.cr1.write(|w| {
w
// clock phase from config
.cpha()
.bit(mode.phase == Phase::CaptureOnSecondTransition)
// clock polarity from config
.cpol()
.bit(mode.polarity == Polarity::IdleHigh)
// mstr: master configuration
.mstr()
.set_bit()
// baudrate value
.br()
.bits(br)
// lsbfirst: MSB first
.lsbfirst()
.clear_bit()
// ssm: enable software slave management (NSS pin free for other uses)
.ssm()
.set_bit()
// ssi: set nss high = master mode
.ssi()
.set_bit()
// dff: 16 bit frames
.dff()
.set_bit()
// bidimode: 2-line unidirectional
.bidimode()
.clear_bit()
// both TX and RX are used
.rxonly()
.clear_bit()
// spe: enable the SPI bus
.spe()
.set_bit()
});

Spi {
spi,
pins,
_remap: PhantomData,
_framesize: PhantomData,
}
}

pub fn frame_size_8bit(self) -> Spi<SPI, REMAP, PINS, u8>{
self.spi.cr1.modify(|_, w| w.spe().clear_bit());
self.spi.cr1.modify(|_, w| w.dff().clear_bit());
self.spi.cr1.modify(|_, w| w.spe().set_bit());
Spi{
spi: self.spi,
pins: self.pins,
_remap: PhantomData,
_framesize: PhantomData,
}
}

Expand All @@ -312,7 +424,7 @@ where
}
}

impl<SPI, REMAP, PINS> crate::hal::spi::FullDuplex<u8> for Spi<SPI, REMAP, PINS>
impl<SPI, REMAP, PINS> crate::hal::spi::FullDuplex<u8> for Spi<SPI, REMAP, PINS, u8>
where
SPI: Deref<Target = SpiRegisterBlock>,
{
Expand Down Expand Up @@ -355,12 +467,60 @@ where
}
}

impl<SPI, REMAP, PINS> crate::hal::blocking::spi::transfer::Default<u8> for Spi<SPI, REMAP, PINS> where
impl<SPI, REMAP, PINS> crate::hal::spi::FullDuplex<u16> for Spi<SPI, REMAP, PINS, u16>
where
SPI: Deref<Target = SpiRegisterBlock>,
{
type Error = Error;

fn read(&mut self) -> nb::Result<u16, Error> {
let sr = self.spi.sr.read();

Err(if sr.ovr().bit_is_set() {
nb::Error::Other(Error::Overrun)
} else if sr.modf().bit_is_set() {
nb::Error::Other(Error::ModeFault)
} else if sr.crcerr().bit_is_set() {
nb::Error::Other(Error::Crc)
} else if sr.rxne().bit_is_set() {
// NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
// reading a half-word)
return Ok(unsafe { ptr::read_volatile(&self.spi.dr as *const _ as *const u16) });
} else {
nb::Error::WouldBlock
})
}

fn send(&mut self, byte: u16) -> nb::Result<(), Error> {
let sr = self.spi.sr.read();

Err(if sr.ovr().bit_is_set() {
nb::Error::Other(Error::Overrun)
} else if sr.modf().bit_is_set() {
nb::Error::Other(Error::ModeFault)
} else if sr.crcerr().bit_is_set() {
nb::Error::Other(Error::Crc)
} else if sr.txe().bit_is_set() {
// NOTE(write_volatile) see note above
unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut u16, byte) }
return Ok(());
} else {
nb::Error::WouldBlock
})
}
}

impl<SPI, REMAP, PINS> crate::hal::blocking::spi::transfer::Default<u8> for Spi<SPI, REMAP, PINS, u8> where
SPI: Deref<Target = SpiRegisterBlock>
{
}

impl<SPI, REMAP, PINS> crate::hal::blocking::spi::Write<u8> for Spi<SPI, REMAP, PINS>
impl<SPI, REMAP, PINS> crate::hal::blocking::spi::transfer::Default<u16> for Spi<SPI, REMAP, PINS, u16> where
SPI: Deref<Target = SpiRegisterBlock>
{
}

impl<SPI, REMAP, PINS> crate::hal::blocking::spi::Write<u8> for Spi<SPI, REMAP, PINS, u8>
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What is the point of this impl block!

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So this I'm not 100% sure on, but my understanding is by throwing in a dummy impl for transfer::Default, it somehow auto-implements the ability to use the transfer method if you also have impl ...::spi::FullDuplex. The current master already has this in there, I just duplicated it for <u8> and <u16> version, but am not certain how it works.

where
SPI: Deref<Target = SpiRegisterBlock>,
{
Expand Down Expand Up @@ -409,10 +569,59 @@ where
}
}

impl<SPI, REMAP, PINS> crate::hal::blocking::spi::Write<u16> for Spi<SPI, REMAP, PINS, u16>
where
SPI: Deref<Target = SpiRegisterBlock>,
{
type Error = Error;

// Implement write as per the "Transmit only procedure" page 712
// of RM0008 Rev 20. This is more than twice as fast as the
// default Write<> implementation (which reads and drops each
// received value)
fn write(&mut self, words: &[u16]) -> Result<(), Error> {
// Write each word when the tx buffer is empty
for word in words {
loop {
let sr = self.spi.sr.read();
if sr.txe().bit_is_set() {
// NOTE(write_volatile) see note above
unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut u16, *word) }
if sr.modf().bit_is_set() {
return Err(Error::ModeFault);
}
break;
}
}
}
// Wait for final TXE
loop {
let sr = self.spi.sr.read();
if sr.txe().bit_is_set() {
break;
}
}
// Wait for final !BSY
loop {
let sr = self.spi.sr.read();
if !sr.bsy().bit_is_set() {
break;
}
}
// Clear OVR set due to dropped received values
// NOTE(read_volatile) see note above
unsafe {
let _ = ptr::read_volatile(&self.spi.dr as *const _ as *const u16);
}
let _ = self.spi.sr.read();
Ok(())
}
}

// DMA

pub struct SpiPayload<SPI, REMAP, PINS> {
spi: Spi<SPI, REMAP, PINS>,
spi: Spi<SPI, REMAP, PINS, u8>,
}

pub type SpiTxDma<SPI, REMAP, PINS, CHANNEL> = TxDma<SpiPayload<SPI, REMAP, PINS>, CHANNEL>;
Expand All @@ -424,7 +633,7 @@ macro_rules! spi_dma {
type ReceivedWord = u8;
}

impl<REMAP, PINS> Spi<$SPIi, REMAP, PINS> {
impl<REMAP, PINS> Spi<$SPIi, REMAP, PINS, u8> {
pub fn with_tx_dma(self, channel: $TCi) -> SpiTxDma<$SPIi, REMAP, PINS, $TCi> {
let payload = SpiPayload { spi: self };
SpiTxDma { payload, channel }
Expand Down