This package provides useful extensions on top of verilog-mode
and verilog-ts-mode
.
- Tree-sitter
verilog-ts-mode
support - Improve syntax highlighting
- Find definitions and references
- Auto-completion with dot and scope completion
- Hierarchy extraction and navigation
- LSP configuration for
lsp-mode
andeglot
- Support for many linters via
flycheck
- Beautify modules and instances
- Code navigation functions for RTL and Verification environments
- Extended collection of templates via
yasnippet
andhydra
- Code formatter via
apheleia
- Compilation with colored errors/warnings and jump to file/line
- Improve
imenu
entries: detect instances, classes and methods - Enhanced support for
which-func
- Code folding via
hideshow
- Highlight and align typedefs
- Auto-configure
time-stamp
- Auto-convert block end comments to names
- Port connection utilities
- Emacs 29.1+
- Latest
verilog-mode
version - Feature-specific binaries
Tree-sitter is optional but recommended and only required if using verilog-ts-mode
for some of the features above.
For more info, see the wiki.
verilog-ext
is available on MELPA.
To install it via straight with use-package
:
(straight-use-package 'use-package)
(use-package verilog-ext)
The most basic configuration just requires choosing which features you
want to load, setup the minor-mode and add it as a hook for verilog-mode
.
By default all features are enabled:
;; Can also be set through `M-x RET customize-group RET verilog-ext':
;; Comment out/remove the ones you do not need
(setq verilog-ext-feature-list
'(font-lock
xref
capf
hierarchy
eglot
lsp
flycheck
beautify
navigation
template
formatter
compilation
imenu
which-func
hideshow
typedefs
time-stamp
block-end-comments
ports))
(require 'verilog-ext)
(verilog-ext-mode-setup)
(add-hook 'verilog-mode-hook #'verilog-ext-mode)
If installed and loaded via use-package
:
(use-package verilog-ext
:hook ((verilog-mode . verilog-ext-mode))
:init
;; Can also be set through `M-x RET customize-group RET verilog-ext':
;; Comment out/remove the ones you do not need
(setq verilog-ext-feature-list
'(font-lock
xref
capf
hierarchy
eglot
lsp
flycheck
beautify
navigation
template
formatter
compilation
imenu
which-func
hideshow
typedefs
time-stamp
block-end-comments
ports))
:config
(verilog-ext-mode-setup))
verilog-ext
relies on the concept of a workspace
to select which files will be analyzed
for navigation, completion, hierarchy extraction, compilation directory, etc...
For example, to analyze all the files inside a Git repo but excluding some 3rd party vendor libraries:
(setq verilog-ext-workspace-ignore-dirs '("/path/to/my/repo/lib1" "/path/to/my/repo/lib2"))
(setq verilog-ext-workspace-ignore-files '("/path/to/my/repo/lib3/lib_file.sv"))
To analyze only files inside rtl/tb directories inside a Git repo, plus a couple of specific ones in other directory:
(setq verilog-ext-workspace-dirs '("/path/to/my/repo/src/rtl" "/path/to/my/repo/src/tb"))
(setq verilog-ext-workspace-extra-files '("/path/to/my/repo/misc/specific_file1.sv" "/path/to/my/repo/misc/specific_file2.sv"))
To override the value of workspace
root inside a Git repo:
(setq verilog-ext-workspace-root-dir "/path/to/my/overriden/workspace/root")
Enabling of verilog-ext-mode
minor-mode creates the following keybindings:
-
Features:
- C-c C-l
verilog-ext-formatter-run
- C-c <f5>
verilog-ext-workspace-compile
- C-c C-p
verilog-ext-preprocess
- C-c C-f
verilog-ext-flycheck-mode
- C-c C-t
verilog-ext-hydra/body
- C-c C-v
verilog-ext-hierarchy-current-buffer
- C-<tab>
verilog-ext-hs-toggle-hiding
- C-c C-l
-
Code beautifying
- C-M-i
verilog-ext-beautify-block-at-point-indent
- C-c C-b
verilog-ext-beautify-module-at-point
- C-M-i
-
Dwim navigation
- C-M-a
verilog-ext-nav-beg-of-defun-dwim
- C-M-e
verilog-ext-nav-end-of-defun-dwim
- C-M-d
verilog-ext-nav-down-dwim
- C-M-u
verilog-ext-nav-up-dwim
- C-M-p
verilog-ext-nav-prev-dwim
- C-M-n
verilog-ext-nav-next-dwim
- C-M-a
-
Module at point
- C-c M-.
verilog-ext-jump-to-module-at-point-def
- C-c M-?
verilog-ext-jump-to-module-at-point-ref
- C-c M-.
-
Jump to parent module
- C-M-.
verilog-ext-workspace-jump-to-parent-module
- C-M-.
-
Port connections
- C-c C-c c
verilog-ext-ports-clean-blanks
- C-c C-c t
verilog-ext-ports-toggle-connect
- C-c C-c r
verilog-ext-ports-connect-recursively
- C-c C-c c
-
Syntax table override functions:
- TAB
verilog-ext-tab
- M-d
verilog-ext-kill-word
- M-f
verilog-ext-forward-word
- M-b
verilog-ext-backward-word
- C-<backspace>
verilog-ext-backward-kill-word
- TAB
Some of the features that verilog-ext
provides are based either on
builtin verilog-mode
Emacs lisp parsing or on tree-sitter
verilog-ts-mode
. These features are hierarchy extraction and workspace
tags collection for completion and navigation of definitions and
references.
Using tree-sitter as a backend is recommended as it is much faster, efficient and accurate than internal Emacs lisp parsing.
For information about installation of verilog-ts-mode
check its
repo.
For configuration information, see the wiki.
verilog-ext
provides an xref
backend to navigate definitions and references of the workspace.
![](https://private-user-images.githubusercontent.com/51021955/243678782-d196a676-6d28-4bfa-9cee-2662d592b3fb.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjQ2ODkzNDYsIm5iZiI6MTcyNDY4OTA0NiwicGF0aCI6Ii81MTAyMTk1NS8yNDM2Nzg3ODItZDE5NmE2NzYtNmQyOC00YmZhLTljZWUtMjY2MmQ1OTJiM2ZiLmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MjYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODI2VDE2MTcyNlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWUyN2ExMTVmYmI2M2Q4NDFkOTRiYjJhMjcwNTNiNDg5N2U4M2YwMDc3Y2ExN2FjZGVhOWM5YWE1MzA1MmIxYzcmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.OST73bm0DiIHFOSq8X39pC5HOvklCUMrDs8PSrAcA7U)
For configuration information, see the wiki.
Complete with tags from current workspace. Supports dot and scope completion for module signals, class attributes and methods.
![](https://private-user-images.githubusercontent.com/51021955/243682584-7e0e6e49-8d5d-4be0-bb61-290c950e8623.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjQ2ODkzNDYsIm5iZiI6MTcyNDY4OTA0NiwicGF0aCI6Ii81MTAyMTk1NS8yNDM2ODI1ODQtN2UwZTZlNDktOGQ1ZC00YmUwLWJiNjEtMjkwYzk1MGU4NjIzLmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MjYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODI2VDE2MTcyNlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTcxOTQyZjNhZGI3NDJhYjVjOGQ2NTYxYzI2YjBkZWQ5ZjQwNzMyMzRiNzA4NjM2YTk3OTQyNWYxYzViNTRkMTcmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.WLbmjb82VdiKE84ah81bVaPiPsKkLpORbDGOQVclZns)
For configuration information, see the wiki.
Hierarchy extraction of module at current buffer.
![](https://private-user-images.githubusercontent.com/51021955/243676959-94e009c3-e61c-496a-bacf-02e7d022157a.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjQ2ODkzNDYsIm5iZiI6MTcyNDY4OTA0NiwicGF0aCI6Ii81MTAyMTk1NS8yNDM2NzY5NTktOTRlMDA5YzMtZTYxYy00OTZhLWJhY2YtMDJlN2QwMjIxNTdhLmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MjYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODI2VDE2MTcyNlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWFiYjAxZTBjZDA5ZjA2NzBlZDdjNDBkNjkxYWE5YzUyODFmNDQ2YjBmMjAxZWM0Yzg5ZjdjZmIwZDQ3NjcxMzImWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.uHydAtZj1bh-UTXMiv9HkmsXgyvduRdFqXajWGC2iRA)
For configuration information, see the wiki.
Auto-configure various SystemVerilog language servers for lsp-mode
and eglot
:
For configuration instructions, see the wiki
Support via flycheck
for the following linters:
For configuration and usage instructions, see the wiki
Indent and align parameters and ports of RTL instances.
Interactive functions:
verilog-ext-beautify-module-at-point
: C-c C-bverilog-ext-beautify-current-buffer
Batch-mode functions:
verilog-ext-beautify-files
verilog-ext-beautify-dir-files
Features:
- Context aware dwim functions for RTL/Verification environments
- Navigate instances inside a module
- Jump to definition/references of module at point
- Jump to parent module
For detailed info see the wiki.
Select among snippets that cover most frequently used SystemVerilog constructs:
Insert instances in current module from file:
Create basic testbench environment from DUT file:
UVM Agent template:
![](https://private-user-images.githubusercontent.com/51021955/259373175-255e4b4b-afb7-4720-8b21-55796ae887eb.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjQ2ODkzNDYsIm5iZiI6MTcyNDY4OTA0NiwicGF0aCI6Ii81MTAyMTk1NS8yNTkzNzMxNzUtMjU1ZTRiNGItYWZiNy00NzIwLThiMjEtNTU3OTZhZTg4N2ViLmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MjYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODI2VDE2MTcyNlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTkwNjUzNDkxMGNjOTI3ZDZmOTdhYTRlNGEzMTBiNGZlMGMzNDBmNmE0MmQxMTc3ODBkYzNmNmVjOWEzMTRhODQmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.iAniJyBxv2AXMe_aCSIMfgOHTWMO8JywUPlF7dzWFYY)
Functions:
verilog-ext-hydra/body
: C-c C-t
Code-formatter setup via apheleia and verible-verilog-format
.
See configuration in the wiki.
Provides functions to perform compilations with syntax highlighting and jump to error, buffer preprocessing and makefile development:
![](https://private-user-images.githubusercontent.com/51021955/243708037-1a78cc1b-da3e-4219-baaf-cb1fb11d335c.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjQ2ODkzNDYsIm5iZiI6MTcyNDY4OTA0NiwicGF0aCI6Ii81MTAyMTk1NS8yNDM3MDgwMzctMWE3OGNjMWItZGEzZS00MjE5LWJhYWYtY2IxZmIxMWQzMzVjLmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MjYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODI2VDE2MTcyNlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWMyOGQ5YjUzNjZiOTVmNzdhNjE2ZTFkODI1MjkwMmE3NTJhNmQzOTcyNmM1NmIzNjhjMDU5YmQ4ZDhhY2M4MGUmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.0IJUXEFaFbg2doIZn1d4VWkE32QxvpIdA85QI6tfEFQ)
verilog-ext-workspace-compile
: C-c <f5>verilog-ext-preprocess
: C-c C-pverilog-ext-workspace-makefile-create
verilog-ext-workspace-makefile-compile
See configuration in the wiki.
Support detection of instances and methods inside classes.
Instances:
Methods:
Find more information here.
Enhanced which-func
support: show current block/instance at point in the mode-line
Code folding via hideshow
: C-<tab>
Add support for syntax-higlighting and alignment via
verilog-pretty-declarations
of user defined types and classes.
![](https://private-user-images.githubusercontent.com/51021955/243712294-5e654ba5-6eaa-4699-865c-628cadeda75a.gif?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjQ2ODkzNDYsIm5iZiI6MTcyNDY4OTA0NiwicGF0aCI6Ii81MTAyMTk1NS8yNDM3MTIyOTQtNWU2NTRiYTUtNmVhYS00Njk5LTg2NWMtNjI4Y2FkZWRhNzVhLmdpZj9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA4MjYlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwODI2VDE2MTcyNlomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPTc0Y2UyMWZkMmU2ZTA4ZGZjZmI0OGFlMjVhMDMxZDA3MTIyOTFiYzgwOWMxNDI4ZDYxMzVkOWM3YjQxNjI2MzAmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.mLraQGXC0stgvPZ-fCXvsnD_R7aWsPGAJaszNbrNxeo)
For configuration see wiki
Automatic update of header timestamp after file saving.
verilog-ext-time-stamp-mode
For configuration see wiki
Auto convert block comments to names after file saving.
verilog-ext-block-end-comments-to-names-mode
Toggle connections of ports under instance at point
verilog-ext-ports-toggle-connect
: C-c C-c tverilog-ext-ports-connect-recursively
: C-c C-c rverilog-ext-ports-clean-blanks
: C-c C-c c
Wrapper functions to stop cursor at underscores without breaking indentation
verilog-ext-forward-word
: M-fverilog-ext-backward-word
: M-bverilog-ext-kill-word
: M-dverilog-ext-backward-kill-word
: C-<backspace> and M-DEL
Contributions are welcome! Just stick to common Elisp conventions and run the ERT suite after testing your changes and before submitting a new PR.
For new functionality add new ERT tests if possible.
Consider sponsoring to help maintaining the project and for the development of new features. Thank you!
To run the whole ERT test suite change directory to the verilog-ext
root and make sure test-hdl
Git submodule has been loaded:
git submodule update --init
Then run the default target:
$ make
To run a subset of tests (e.g. navigation):
$ make TESTS=navigation
To regenerate all the expected outputs for the tests:
$ make gen
To regenerate the expected outputs for a group of tests (e.g. navigation):
$ make gen TESTS=navigation
- verilog-ts-mode: SystemVerilog Tree-sitter mode
- vhdl-ts-mode: VHDL Tree-sitter mode
- vhdl-ext: VHDL Extensions
- fpga: FPGA & ASIC Utilities for tools of major vendors and open source
- wavedrom-mode: edit and render WaveJSON files to create timing diagrams
- vunit-mode: Integration of VUnit workflow