[platform]Accton, add platform as6712-32x. (#2178)

* [platform] Add 6712 dpkg on building.
Signed-off-by: roy_lee <[email protected]>

* [platform] remove scache_filename for it failed the bcm checker.
Signed-off-by: roy_lee <[email protected]>

* [plaform] add platform/device as6712-32x.
Signed-off-by: roy_lee <[email protected]>

* [platform] fix error on private data reference at cpld.c.
Signed-off-by: roy_lee <[email protected]>

device/accton/x86_64-accton_as6712_32x-r0/Accton-AS6712-32X/port_config.ini

@@ -0,0 +1,33 @@
+# name          lanes                 alias
+Ethernet0       49,50,51,52           fortyGigE1
+Ethernet4       53,54,55,56           fortyGigE2
+Ethernet8       57,58,59,60           fortyGigE3
+Ethernet12      61,62,63,64           fortyGigE4
+Ethernet16      65,66,67,68           fortyGigE5
+Ethernet20      69,70,71,72           fortyGigE6
+Ethernet24      73,74,75,76           fortyGigE7
+Ethernet28      77,78,79,80           fortyGigE8
+Ethernet32      33,34,35,36           fortyGigE9
+Ethernet36      37,38,39,40           fortyGigE10
+Ethernet40      41,42,43,44           fortyGigE11
+Ethernet44      45,46,47,48           fortyGigE12
+Ethernet48      81,82,83,84           fortyGigE13
+Ethernet52      85,86,87,88           fortyGigE14
+Ethernet56      89,90,91,92           fortyGigE15
+Ethernet60      93,94,95,96           fortyGigE16
+Ethernet64      97,98,99,100          fortyGigE17
+Ethernet68      101,102,103,104       fortyGigE18
+Ethernet72      105,106,107,108       fortyGigE19
+Ethernet76      109,110,111,112       fortyGigE20
+Ethernet80      17,18,19,20           fortyGigE21
+Ethernet84      21,22,23,24           fortyGigE22
+Ethernet88      25,26,27,28           fortyGigE23
+Ethernet92      29,30,31,32           fortyGigE24
+Ethernet96      113,114,115,116       fortyGigE25
+Ethernet100     117,118,119,120       fortyGigE26
+Ethernet104     121,122,123,124       fortyGigE27
+Ethernet108     125,126,127,128       fortyGigE28
+Ethernet112     1,2,3,4               fortyGigE29
+Ethernet116     5,6,7,8               fortyGigE30
+Ethernet120     9,10,11,12            fortyGigE31
+Ethernet124     13,14,15,16           fortyGigE32

device/accton/x86_64-accton_as6712_32x-r0/Accton-AS6712-32X/sai.profile

@@ -0,0 +1 @@
+SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/td2-as6712-32x40G.config.bcm

device/accton/x86_64-accton_as6712_32x-r0/Accton-AS6712-32X/td2-as6712-32x40G.config.bcm

@@ -0,0 +1,132 @@
+os=unix
+bcm_stat_flags=0
+parity_enable=0
+parity_correction=0
+
+l2_mem_entries=163840
+l3_mem_entries=81920
+mmu_lossless=0
+lls_num_l2uc=12
+module_64ports=0
+
+#SFI
+serdes_if_type=9
+
+port_init_cl72=0
+phy_an_c73=5 # TSCMOD_CL73_CL37
+
+#sdk6.5.5 only supports 156(default) or 125
+#xgxs_lcpll_xtal_refclk=1
+tslam_dma_enable=1
+table_dma_enable=1
+
+#for 32x40G ports for breakout mode
+pbmp_oversubscribe=0x1fffffffe
+pbmp_xport_xe=0x1fffffffe
+
+rate_ext_mdio_divisor=96
+
+#QSFP+ 1 from WC0
+portmap_1=1:40
+
+#QSFP+ 2 from WC1
+portmap_2=5:40
+
+#QSFP+ 3 from WC2
+portmap_3=9:40
+
+#QSFP+ 4 from WC3
+portmap_4=13:40
+
+#QSFP+ 5 from WC4
+portmap_5=17:40
+
+#QSFP+ 6 from WC5
+portmap_6=21:40
+
+#QSFP+ 7 from WC6
+portmap_7=25:40
+
+#QSFP+ 8 from WC7
+portmap_8=29:40
+
+#QSFP+ 9 from WC8
+portmap_9=33:40
+
+#QSFP+ 10 from WC9
+portmap_10=37:40
+
+#QSFP+ 11 from WC10
+portmap_11=41:40
+
+#QSFP+ 12 from WC11
+portmap_12=45:40
+
+#QSFP+ 13 from WC12
+portmap_13=49:40
+
+#QSFP+ 14 from WC13
+portmap_14=53:40
+
+#QSFP+ 15 from WC14
+portmap_15=57:40
+
+#QSFP+ 16 from WC15
+portmap_16=61:40
+
+#QSFP+ 17 from WC16
+portmap_17=65:40
+
+#QSFP+ 18 from WC17
+portmap_18=69:40
+
+#QSFP+ 19 from WC18
+portmap_19=73:40
+
+#QSFP+ 20 from WC19
+portmap_20=77:40
+
+#QSFP+ 21 from WC20
+portmap_21=81:40
+
+#QSFP+ 22 from WC21
+portmap_22=85:40
+
+#QSFP+ 23 from WC22
+portmap_23=89:40
+
+#QSFP+ 24 from WC23
+portmap_24=93:40
+
+#QSFP+ 25 from WC24
+portmap_25=97:40
+
+#QSFP+ 26 from WC25
+portmap_26=101:40
+
+#QSFP+ 27 from WC26
+portmap_27=105:40
+
+#QSFP+ 28 from WC27
+portmap_28=109:40
+
+#QSFP+ 29 from WC28
+portmap_29=113:40
+
+#QSFP+ 30 from WC29
+portmap_30=117:40
+
+#QSFP+ 31 from WC30
+portmap_31=121:40
+
+#QSFP+ 32 from WC31
+portmap_32=125:40
+
+# L3 ECMP
+# - In Trident2, VP LAGs share the same table as ECMP group table.
+#   The first N entries are reserved for VP LAGs, where N is the value of the
+#   config property "max_vp_lags". By default this was set to 256
+l3_max_ecmp_mode=1
+max_vp_lags=0
+
+stable_size=0x2000000

device/accton/x86_64-accton_as6712_32x-r0/default_sku

@@ -0,0 +1 @@
+Accton-AS6712-32X t1

device/accton/x86_64-accton_as6712_32x-r0/installer.conf

@@ -0,0 +1,3 @@
+CONSOLE_PORT=0x2f8
+CONSOLE_DEV=1
+CONSOLE_SPEED=115200

device/accton/x86_64-accton_as6712_32x-r0/led_proc_init.soc

@@ -0,0 +1,104 @@
+# LED setting for active
+# -----------------------------------------------------------------------------
+# for as6712_32x (32 qxg)
+# -----------------------------------------------------------------------------
+
+s CMIC_LEDUP0_DATA_RAM 0
+s CMIC_LEDUP1_DATA_RAM 0
+
+m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_63=0
+m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_59=1
+m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_55=2
+m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_51=3
+m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_35=4
+m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_39=5
+m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_43=6
+m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_47=7
+
+m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_31=8
+m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_27=9
+m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_23=10
+m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_19=11
+m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_3=12
+m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_7=13
+m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_11=14
+m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_15=15
+
+
+m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_62=63
+m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_61=62
+m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=61
+m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_58=60
+m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_57=59
+m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=58
+m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_54=57
+m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_53=56
+m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=55
+m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_50=54
+m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_49=53
+m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=52
+m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_46=51
+m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_45=50
+m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=49
+m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_42=48
+m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_41=47
+m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=46
+m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_38=45
+m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_37=44
+m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=43
+m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_34=42
+m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_33=41
+m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=40
+m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_30=39
+m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_29=38
+m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=37
+m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_26=36
+m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_25=35
+m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=34
+m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_22=33
+m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_21=32
+m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=31
+m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_18=30
+m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_17=29
+m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=28
+m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_14=27
+m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_13=26
+m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=25
+m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_10=24
+m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_9=23
+m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=22
+m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_6=21
+m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_5=20
+m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=19
+m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_2=18
+m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_1=17
+m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=16
+
+
+led 0 stop
+led 0 prog \
+ 02 F9 42 80 02 F7 42 00 02 F8 42 00 02 F4 42 90 02 \
+ F3 42 10 67 6A 67 6A 67 38 67 6A 67 6A 67 6A 67 6A \
+ 67 6A 67 6A 86 F8 06 F3 D6 F8 74 14 86 F0 3E F4 67 \
+ 6A 57 67 7E 57 06 F8 88 80 4A 00 27 97 75 35 90 4A \
+ 00 27 4A 01 27 B7 97 71 4F 77 32 06 F5 D6 F0 74 62 \
+ 02 F5 4A 07 37 4E 07 02 F0 42 00 4E 07 02 F5 4A 07 \
+ 71 32 77 35 16 F7 06 F9 17 4D DA 07 74 7B 12 F7 52 \
+ 00 86 F9 57 86 F7 57 16 F7 06 F9 07 4D DA 07 74 8F \
+ 12 F7 52 00 86 F9 57 86 F7 57 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00
+led 0 start
+
+led 1 stop
+led 1 prog \
+ 02 F9 42 80 02 F7 42 00 02 F8 42 01 02 F4 42 90 02 \
+ F3 42 11 67 6A 67 6A 67 38 67 6A 67 6A 67 6A 67 6A \
+ 67 6A 67 6A 86 F8 06 F3 D6 F8 74 14 86 F0 3E F4 67 \
+ 6A 57 67 7E 57 06 F8 88 80 4A 00 27 97 75 35 90 4A \
+ 00 27 4A 01 27 B7 97 71 4F 77 32 06 F5 D6 F0 74 62 \
+ 02 F5 4A 07 37 4E 07 02 F0 42 00 4E 07 02 F5 4A 07 \
+ 71 32 77 35 16 F7 06 F9 17 4D DA 07 74 7B 12 F7 52 \
+ 00 86 F9 57 86 F7 57 16 F7 06 F9 07 4D DA 07 74 8F \
+ 12 F7 52 00 86 F9 57 86 F7 57 00 00 00 00 00 00 00 \
+ 00 00 00 00 00 00 00
+led 1 start

device/accton/x86_64-accton_as6712_32x-r0/plugins/eeprom.py

@@ -0,0 +1,24 @@
+#!/usr/bin/env python
+
+try:
+    import exceptions
+    import binascii
+    import time
+    import optparse
+    import warnings
+    import os
+    import sys
+    from sonic_eeprom import eeprom_base
+    from sonic_eeprom import eeprom_tlvinfo
+    import subprocess
+except ImportError, e:
+    raise ImportError (str(e) + "- required module not found")
+
+class board(eeprom_tlvinfo.TlvInfoDecoder):
+    _TLV_INFO_MAX_LEN = 256
+    def __init__(self, name, path, cpld_root, ro):
+        self.eeprom_path = "/sys/bus/i2c/devices/1-0057/eeprom"
+        #Two i2c buses might get flipped order, check them both.
+        if not os.path.exists(self.eeprom_path):
+            self.eeprom_path = "/sys/bus/i2c/devices/0-0057/eeprom"
+        super(board, self).__init__(self.eeprom_path, 0, '', True)

device/accton/x86_64-accton_as6712_32x-r0/plugins/psuutil.py

@@ -0,0 +1,61 @@
+#!/usr/bin/env python
+
+#############################################################################
+# Accton
+#
+# Module contains an implementation of SONiC PSU Base API and
+# provides the PSUs status which are available in the platform
+#
+#############################################################################
+
+import os.path
+
+try:
+    from sonic_psu.psu_base import PsuBase
+except ImportError as e:
+    raise ImportError (str(e) + "- required module not found")
+
+class PsuUtil(PsuBase):
+    """Platform-specific PSUutil class"""
+
+    def __init__(self):
+        PsuBase.__init__(self)
+
+        self.psu_path = "/sys/bus/i2c/devices/"
+        self.psu_presence = "/psu_present"
+        self.psu_oper_status = "/psu_power_good"
+        self.psu_mapping = {
+            1: "35-0038",
+            2: "36-003b",
+        }
+
+    def get_num_psus(self):
+        return len(self.psu_mapping)
+
+    def get_psu_status(self, index):
+        if index is None:
+            return False
+
+        status = 0
+        node = self.psu_path + self.psu_mapping[index]+self.psu_oper_status
+        try:
+            with open(node, 'r') as power_status:
+                status = int(power_status.read())
+        except IOError:
+            return False
+
+        return status == 1
+
+    def get_psu_presence(self, index):
+        if index is None:
+            return False
+
+        status = 0
+        node = self.psu_path + self.psu_mapping[index] + self.psu_presence
+        try:
+            with open(node, 'r') as presence_status:
+                status = int(presence_status.read())
+        except IOError:
+            return False
+
+        return status == 1