Merge branch 'master' into syncd_bullseye_merge_2

sonic-net · Apr 15, 2022 · 7279797 · 7279797
2 parents 7c09e36 + d9117d9
commit 7279797
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diff --git a/build_debian.sh b/build_debian.sh
@@ -447,7 +447,7 @@ sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install 'setup
 sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install 'wheel==0.35.1'
 
 # docker Python API package is needed by Ansible docker module as well as some SONiC applications
-sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install 'docker==4.3.1'
+sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install 'docker==5.0.3'
 
 # Install scapy
 sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install 'scapy==2.4.4'

diff --git a/...ista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/td3-a7050cx3-32s-32x100G.config.bcm b/...ista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/td3-a7050cx3-32s-32x100G.config.bcm
@@ -5,6 +5,7 @@ host_as_route_disable=1
 use_all_splithorizon_groups=1
 riot_enable=1
 sai_tunnel_support=1
+sai_tunnel_underlay_route_mode=1
 riot_overlay_l3_intf_mem_size=4096
 riot_overlay_l3_egress_mem_size=32768
 l3_ecmp_levels=2

diff --git a/..._64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/td3-a7050cx3-32s-48x50G+8x100G.config.bcm b/..._64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/td3-a7050cx3-32s-48x50G+8x100G.config.bcm
@@ -5,6 +5,7 @@ host_as_route_disable=1
 use_all_splithorizon_groups=1
 riot_enable=1
 sai_tunnel_support=1
+sai_tunnel_underlay_route_mode=1
 riot_overlay_l3_intf_mem_size=4096
 riot_overlay_l3_egress_mem_size=32768
 l3_ecmp_levels=2

diff --git a/device/arista/x86_64-arista_7050cx3_32s/td3-a7050cx3-32s-flex.config.bcm b/device/arista/x86_64-arista_7050cx3_32s/td3-a7050cx3-32s-flex.config.bcm
@@ -397,6 +397,7 @@ robust_hash_disable_mpls=1
 robust_hash_disable_vlan=1
 sai_load_hw_config=/etc/bcm/flex/bcm56870_a0_premium_issu/b870.6.4.1/
 sai_tunnel_support=1
+sai_tunnel_underlay_route_mode=1
 serdes_core_rx_polarity_flip_physical{1}=0x8
 serdes_core_rx_polarity_flip_physical{5}=0x2
 serdes_core_rx_polarity_flip_physical{9}=0xc

diff --git a/device/arista/x86_64-arista_7170_64c/Arista-7170-64C/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7170_64c/Arista-7170-64C/buffers_defaults_t0.j2
@@ -61,11 +61,15 @@
 
 {%- macro generate_queue_buffers(port_names) %}
     "BUFFER_QUEUE": {
-        "{{ port_names }}|3-4": {
-            "profile" : "egress_lossless_profile"
-        },
-        "{{ port_names }}|0-1": {
+{% for port in port_names.split(',') %}
+        "{{ port }}|0-2": {
             "profile" : "q_lossy_profile"
-        }
+        },
+{% endfor %}
+{% for port in port_names.split(',') %}
+        "{{ port }}|3-4": {
+            "profile" : "egress_lossless_profile"
+        }{% if not loop.last %},{% endif %}
+{% endfor %}
     }
 {%- endmacro %}
diff --git a/device/arista/x86_64-arista_7170_64c/Arista-7170-64C/buffers_defaults_t1.j2 b/device/arista/x86_64-arista_7170_64c/Arista-7170-64C/buffers_defaults_t1.j2
@@ -61,11 +61,15 @@
 
 {%- macro generate_queue_buffers(port_names) %}
     "BUFFER_QUEUE": {
-        "{{ port_names }}|3-4": {
-            "profile" : "egress_lossless_profile"
-        },
-        "{{ port_names }}|0-1": {
+{% for port in port_names.split(',') %}
+        "{{ port }}|0-2": {
             "profile" : "q_lossy_profile"
-        }
+        },
+{% endfor %}
+{% for port in port_names.split(',') %}
+        "{{ port }}|3-4": {
+            "profile" : "egress_lossless_profile"
+        }{% if not loop.last %},{% endif %}
+{% endfor %}
     }
 {%- endmacro %}
diff --git a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-C64/config.bcm.j2 b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-C64/config.bcm.j2
@@ -12,6 +12,7 @@
 {%-         set switch_subtype = DEVICE_METADATA['localhost']['subtype'] -%}
 {%-         if 'dualtor' in switch_subtype.lower() %}
 {%-             set IPinIP_sock = 'sai_tunnel_support=1
+                                   sai_tunnel_underlay_route_mode=1
                                    host_as_route_disable=1
                                    l3_ecmp_levels=2' -%}
 {%-         endif %}

diff --git a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C8/config.bcm.j2 b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C8/config.bcm.j2
@@ -4,6 +4,7 @@
 {%-     set switch_subtype = DEVICE_METADATA['localhost']['subtype'] -%}
 {%-     if 'dualtor' in switch_subtype.lower() %}
 {%-         set IPinIP_sock = 'sai_tunnel_support=1
+                               sai_tunnel_underlay_route_mode=1
                                host_as_route_disable=1
                                l3_ecmp_levels=2' -%}
 {%-     endif %}

diff --git a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/config.bcm.j2 b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/config.bcm.j2
@@ -12,6 +12,7 @@
 {%-         set switch_subtype = DEVICE_METADATA['localhost']['subtype'] -%}
 {%-         if 'dualtor' in switch_subtype.lower() %}
 {%-             set IPinIP_sock = 'sai_tunnel_support=1
+                                   sai_tunnel_underlay_route_mode=1
                                    host_as_route_disable=1
                                    l3_ecmp_levels=2' -%}
 {%-         endif %}

diff --git a/...86_64-arista_7800r3_48cq2_lc/Arista-7800R3-48CQ2-C48/jr2-a7280cr3-32d4-40x100G.config.bcm b/...86_64-arista_7800r3_48cq2_lc/Arista-7800R3-48CQ2-C48/jr2-a7280cr3-32d4-40x100G.config.bcm
@@ -362,6 +362,55 @@ ucode_port_46=CGE2_25:core_1.46
 ucode_port_47=CGE2_26:core_1.47
 ucode_port_48=CGE2_24:core_1.48
 
+serdes_tx_taps_1=pam4:-18:86:0:4:0:0
+serdes_tx_taps_2=pam4:-18:86:0:4:0:0
+serdes_tx_taps_3=pam4:-18:86:0:4:0:0
+serdes_tx_taps_4=pam4:-18:86:0:4:0:0
+serdes_tx_taps_5=pam4:-18:86:0:4:0:0
+serdes_tx_taps_6=pam4:-18:86:0:4:0:0
+serdes_tx_taps_7=pam4:-18:86:0:4:0:0
+serdes_tx_taps_8=pam4:-18:86:0:4:0:0
+serdes_tx_taps_9=pam4:-18:86:0:4:0:0
+serdes_tx_taps_10=pam4:-18:86:0:4:0:0
+serdes_tx_taps_11=pam4:-18:86:0:4:0:0
+serdes_tx_taps_12=pam4:-18:86:0:4:0:0
+serdes_tx_taps_13=pam4:-18:86:0:4:0:0
+serdes_tx_taps_14=pam4:-18:86:0:4:0:0
+serdes_tx_taps_15=pam4:-18:86:0:4:0:0
+serdes_tx_taps_16=pam4:-18:86:0:4:0:0
+serdes_tx_taps_17=pam4:-18:86:0:4:0:0
+serdes_tx_taps_18=pam4:-18:86:0:4:0:0
+serdes_tx_taps_19=pam4:-18:86:0:4:0:0
+serdes_tx_taps_20=pam4:-18:86:0:4:0:0
+serdes_tx_taps_21=pam4:-18:86:0:4:0:0
+serdes_tx_taps_22=pam4:-18:86:0:4:0:0
+serdes_tx_taps_23=pam4:-18:86:0:4:0:0
+serdes_tx_taps_24=pam4:-18:86:0:4:0:0
+serdes_tx_taps_25=pam4:-18:86:0:4:0:0
+serdes_tx_taps_26=pam4:-18:86:0:4:0:0
+serdes_tx_taps_27=pam4:-18:86:0:4:0:0
+serdes_tx_taps_28=pam4:-18:86:0:4:0:0
+serdes_tx_taps_29=pam4:-18:86:0:4:0:0
+serdes_tx_taps_30=pam4:-18:86:0:4:0:0
+serdes_tx_taps_31=pam4:-18:86:0:4:0:0
+serdes_tx_taps_32=pam4:-18:86:0:4:0:0
+serdes_tx_taps_33=pam4:-18:86:0:4:0:0
+serdes_tx_taps_34=pam4:-18:86:0:4:0:0
+serdes_tx_taps_35=pam4:-18:86:0:4:0:0
+serdes_tx_taps_36=pam4:-18:86:0:4:0:0
+serdes_tx_taps_37=pam4:-18:86:0:4:0:0
+serdes_tx_taps_38=pam4:-18:86:0:4:0:0
+serdes_tx_taps_39=pam4:-18:86:0:4:0:0
+serdes_tx_taps_40=pam4:-18:86:0:4:0:0
+serdes_tx_taps_41=pam4:-18:86:0:4:0:0
+serdes_tx_taps_42=pam4:-18:86:0:4:0:0
+serdes_tx_taps_43=pam4:-18:86:0:4:0:0
+serdes_tx_taps_44=pam4:-18:86:0:4:0:0
+serdes_tx_taps_45=pam4:-18:86:0:4:0:0
+serdes_tx_taps_46=pam4:-18:86:0:4:0:0
+serdes_tx_taps_47=pam4:-18:86:0:4:0:0
+serdes_tx_taps_48=pam4:-18:86:0:4:0:0
+
 ucode_port_0.BCM8869X=CPU.0:core_0.0
 ucode_port_200.BCM8869X=CPU.8:core_1.200
 ucode_port_201.BCM8869X=CPU.16:core_0.201

diff --git a/device/arista/x86_64-arista_7800r3_48cqm2_lc/Arista-7800R3-48CQM2-C48/gearbox_100G_PAM4.xml b/device/arista/x86_64-arista_7800r3_48cqm2_lc/Arista-7800R3-48CQM2-C48/gearbox_100G_PAM4.xml
@@ -4,11 +4,6 @@
     <phy_addr>0</phy_addr>
     <mode>gearbox</mode>
     <topology>2</topology>
-    <tx-taps>
-        <PAM4>2,-8,17,0,0</PAM4>
-        <NRZ>0,-8,17,0,0</NRZ>
-    </tx-taps>
-    <tx-taps-scale>0,0,1,0,0</tx-taps-scale>
 
     <lane id="0" system-side="true" />
     <lane id="1" system-side="true" />
@@ -34,4 +29,33 @@
     <lane id="21" system-side="false"  />
     <lane id="22" system-side="false"  />
     <lane id="23" system-side="false"  />
+
+    <PAM4>
+        <lane id="0" tx-taps="1,-5,15,0,0"/>
+        <lane id="1" tx-taps="1,-5,15,0,0"/>
+        <lane id="2" tx-taps="1,-5,15,0,0"/>
+        <lane id="3" tx-taps="1,-5,15,0,0"/>
+        <lane id="4" tx-taps="1,-5,15,0,0"/>
+        <lane id="5" tx-taps="1,-5,15,0,0"/>
+        <lane id="6" tx-taps="1,-5,15,0,0"/>
+        <lane id="7" tx-taps="1,-5,15,0,0"/>
+    </PAM4>
+    <NRZ>
+        <lane id="8" tx-taps="0,-1,15,-6,0"/>
+        <lane id="9" tx-taps="0,-1,15,-6,0"/>
+        <lane id="10" tx-taps="0,-1,15,-6,0"/>
+        <lane id="11" tx-taps="0,-1,15,-6,0"/>
+        <lane id="12" tx-taps="0,-1,15,-6,0"/>
+        <lane id="13" tx-taps="0,-1,15,-6,0"/>
+        <lane id="14" tx-taps="0,-1,15,-6,0"/>
+        <lane id="15" tx-taps="0,-1,15,-6,0"/>
+        <lane id="16" tx-taps="0,-1,15,-6,0"/>
+        <lane id="17" tx-taps="0,-1,15,-6,0"/>
+        <lane id="18" tx-taps="0,-1,15,-6,0"/>
+        <lane id="19" tx-taps="0,-1,15,-6,0"/>
+        <lane id="20" tx-taps="0,-1,15,-6,0"/>
+        <lane id="21" tx-taps="0,-1,15,-6,0"/>
+        <lane id="22" tx-taps="0,-1,15,-6,0"/>
+        <lane id="23" tx-taps="0,-1,15,-6,0"/>
+    </NRZ>
 </root>
diff --git a/device/barefoot/x86_64-accton_as9516_32d-r0/newport/buffers_defaults_t0.j2 b/device/barefoot/x86_64-accton_as9516_32d-r0/newport/buffers_defaults_t0.j2
@@ -16,8 +16,7 @@
         "ingress_lossless_pool": {
             "size": "{{ ingress_lossless_pool_size }}",
             "type": "ingress",
-            "mode": "dynamic",
-            "xoff": "36222208"
+            "mode": "dynamic"
         },
         "ingress_lossy_pool": {
             "size": "{{ ingress_lossy_pool_size }}",
@@ -61,11 +60,15 @@
 
 {%- macro generate_queue_buffers(port_names) %}
     "BUFFER_QUEUE": {
-        "{{ port_names }}|3-4": {
-            "profile" : "egress_lossless_profile"
-        },
-        "{{ port_names }}|0-1": {
+{% for port in port_names.split(',') %}
+        "{{ port }}|0-2": {
             "profile" : "q_lossy_profile"
-        }
+        },
+{% endfor %}
+{% for port in port_names.split(',') %}
+        "{{ port }}|3-4": {
+            "profile" : "egress_lossless_profile"
+        }{% if not loop.last %},{% endif %}
+{% endfor %}
     }
 {%- endmacro %}
diff --git a/device/barefoot/x86_64-accton_as9516_32d-r0/newport/buffers_defaults_t1.j2 b/device/barefoot/x86_64-accton_as9516_32d-r0/newport/buffers_defaults_t1.j2
@@ -16,8 +16,7 @@
         "ingress_lossless_pool": {
             "size": "{{ ingress_lossless_pool_size }}",
             "type": "ingress",
-            "mode": "dynamic",
-            "xoff": "36222208"
+            "mode": "dynamic"
         },
         "ingress_lossy_pool": {
             "size": "{{ ingress_lossy_pool_size }}",
@@ -61,11 +60,15 @@
 
 {%- macro generate_queue_buffers(port_names) %}
     "BUFFER_QUEUE": {
-        "{{ port_names }}|3-4": {
-            "profile" : "egress_lossless_profile"
-        },
-        "{{ port_names }}|0-1": {
+{% for port in port_names.split(',') %}
+        "{{ port }}|0-2": {
             "profile" : "q_lossy_profile"
-        }
+        },
+{% endfor %}
+{% for port in port_names.split(',') %}
+        "{{ port }}|3-4": {
+            "profile" : "egress_lossless_profile"
+        }{% if not loop.last %},{% endif %}
+{% endfor %}
     }
 {%- endmacro %}
diff --git a/device/barefoot/x86_64-accton_wedge100bf_32x-r0/montara/buffers_defaults_t0.j2 b/device/barefoot/x86_64-accton_wedge100bf_32x-r0/montara/buffers_defaults_t0.j2
@@ -63,21 +63,17 @@
     },
 {%- endmacro %}
 
-{%- macro generate_pg_profils(port_names) %}
-    "BUFFER_PG": {
-        "{{ port_names }}|3-4": {
-            "profile" : "ingress_lossless_profile"
-        }
-    },
-{%- endmacro %}
-
 {%- macro generate_queue_buffers(port_names) %}
     "BUFFER_QUEUE": {
-        "{{ port_names }}|3-4": {
-            "profile" : "egress_lossless_profile"
-        },
-        "{{ port_names }}|0-1": {
+{% for port in port_names.split(',') %}
+        "{{ port }}|0-2": {
             "profile" : "q_lossy_profile"
-        }
+        },
+{% endfor %}
+{% for port in port_names.split(',') %}
+        "{{ port }}|3-4": {
+            "profile" : "egress_lossless_profile"
+        }{% if not loop.last %},{% endif %}
+{% endfor %}
     }
 {%- endmacro %}
diff --git a/device/barefoot/x86_64-accton_wedge100bf_32x-r0/montara/buffers_defaults_t1.j2 b/device/barefoot/x86_64-accton_wedge100bf_32x-r0/montara/buffers_defaults_t1.j2
@@ -63,21 +63,17 @@
     },
 {%- endmacro %}
 
-{%- macro generate_pg_profils(port_names) %}
-    "BUFFER_PG": {
-        "{{ port_names }}|3-4": {
-            "profile" : "ingress_lossless_profile"
-        }
-    },
-{%- endmacro %}
-
 {%- macro generate_queue_buffers(port_names) %}
     "BUFFER_QUEUE": {
-        "{{ port_names }}|3-4": {
-            "profile" : "egress_lossless_profile"
-        },
-        "{{ port_names }}|0-1": {
+{% for port in port_names.split(',') %}
+        "{{ port }}|0-2": {
             "profile" : "q_lossy_profile"
-        }
+        },
+{% endfor %}
+{% for port in port_names.split(',') %}
+        "{{ port }}|3-4": {
+            "profile" : "egress_lossless_profile"
+        }{% if not loop.last %},{% endif %}
+{% endfor %}
     }
 {%- endmacro %}
diff --git a/device/mellanox/x86_64-mlnx_msn3700-r0/sensors.conf b/device/mellanox/x86_64-mlnx_msn3700-r0/sensors.conf
@@ -85,6 +85,9 @@ bus "i2c-4" "i2c-1-mux (chan_id 3)"
         label power2 "PSU-2 12V Rail Pwr (out)"
         label curr1 "PSU-2 220V Rail Curr (in)"
         label curr2 "PSU-2 12V Rail Curr (out)"
+        set in3_lcrit in3_crit * 0.662
+        set in3_min in3_crit * 0.745
+        set in3_max in3_crit * 0.952
     chip "dps460-i2c-*-59"
         label in1 "PSU-1 220V Rail (in)"
         ignore in2
@@ -99,6 +102,9 @@ bus "i2c-4" "i2c-1-mux (chan_id 3)"
         label power2 "PSU-1 12V Rail Pwr (out)"
         label curr1 "PSU-1 220V Rail Curr (in)"
         label curr2 "PSU-1 12V Rail Curr (out)"
+        set in3_lcrit in3_crit * 0.662
+        set in3_min in3_crit * 0.745
+        set in3_max in3_crit * 0.952
 
 # Chassis fans
 chip "mlxreg_fan-isa-*"

diff --git a/device/mellanox/x86_64-mlnx_msn3700c-r0/sensors.conf b/device/mellanox/x86_64-mlnx_msn3700c-r0/sensors.conf
@@ -85,6 +85,9 @@ bus "i2c-4" "i2c-1-mux (chan_id 3)"
         label power2 "PSU-2 12V Rail Pwr (out)"
         label curr1 "PSU-2 220V Rail Curr (in)"
         label curr2 "PSU-2 12V Rail Curr (out)"
+        set in3_lcrit in3_crit * 0.662
+        set in3_min in3_crit * 0.745
+        set in3_max in3_crit * 0.952
     chip "dps460-i2c-*-59"
         label in1 "PSU-1 220V Rail (in)"
         ignore in2
@@ -99,6 +102,9 @@ bus "i2c-4" "i2c-1-mux (chan_id 3)"
         label power2 "PSU-1 12V Rail Pwr (out)"
         label curr1 "PSU-1 220V Rail Curr (in)"
         label curr2 "PSU-1 12V Rail Curr (out)"
+        set in3_lcrit in3_crit * 0.662
+        set in3_min in3_crit * 0.745
+        set in3_max in3_crit * 0.952
 
 # Chassis fans
 chip "mlxreg_fan-isa-*"

diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/sensors.conf b/device/mellanox/x86_64-mlnx_msn3800-r0/sensors.conf
@@ -106,6 +106,9 @@ bus "i2c-4" "i2c-1-mux (chan_id 3)"
         label power2 "PSU-2 12V Rail Pwr (out)"
         label curr1 "PSU-2 220V Rail Curr (in)"
         label curr2 "PSU-2 12V Rail Curr (out)"
+        set in3_lcrit in3_crit * 0.662
+        set in3_min in3_crit * 0.745
+        set in3_max in3_crit * 0.952
     chip "dps460-i2c-*-59"
         label in1 "PSU-1 220V Rail (in)"
         ignore in2
@@ -120,6 +123,9 @@ bus "i2c-4" "i2c-1-mux (chan_id 3)"
         label power2 "PSU-1 12V Rail Pwr (out)"
         label curr1 "PSU-1 220V Rail Curr (in)"
         label curr2 "PSU-1 12V Rail Curr (out)"
+        set in3_lcrit in3_crit * 0.662
+        set in3_min in3_crit * 0.745
+        set in3_max in3_crit * 0.952
 
 # Chassis fans
 chip "mlxreg_fan-isa-*"