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@sisshiki1969
sisshiki1969 committed Jan 30, 2025
2 parents 338e92b + a9cd0fc commit 276207f
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Showing 9 changed files with 124 additions and 175 deletions.
2 changes: 0 additions & 2 deletions .vscode/settings.json
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Original file line number Diff line number Diff line change
Expand Up @@ -49,8 +49,6 @@
"./Cargo.toml"
],
"rust-analyzer.showUnlinkedFileNotification": false,
"rust-analyzer.cargo.buildScripts.overrideCommand": null,
"rust-analyzer.cargo.features": "all",
"editor.formatOnSave": true,
"editor.formatOnPaste": true,
}
47 changes: 16 additions & 31 deletions monoruby/src/compiler/jitgen.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -31,18 +31,6 @@ mod slot;
pub mod trace_ir;
mod variables;

struct ContinuationInfo {
from: BBContext,
to: BBContext,
pc: BytecodePtr,
}

impl ContinuationInfo {
fn new(from: BBContext, to: BBContext, pc: BytecodePtr) -> Self {
Self { from, to, pc }
}
}

///
/// Compile result of the current instruction.
///
Expand All @@ -67,16 +55,21 @@ struct JitLabel(usize);
#[derive(Debug, PartialEq)]
enum BranchMode {
///
/// continuation branch.
/// Continuation branch.
///
/// 'continuation' means the destination is adjacent to the source basic block on the bytecode.
///
Continue { dest: JitLabel },
Continue,
///
/// Side branch. (conditional branch)
///
/// side branch. (conditional branch)
/// The machine code for the branch is outlined.
///
Side { dest: JitLabel },
///
/// branch. (unconditional branch)
/// Branch. (unconditional branch)
///
/// The machine code for the branch is inlined.
///
Branch,
}
Expand All @@ -90,11 +83,9 @@ struct BranchEntry {
src_bb: BasicBlockId,
/// context of the source basic block.
bbctx: BBContext,
/// `DestLabel` for the destination basic block.
branch_dest: JitLabel,
/// true if the branch is a continuation branch.
/// 'continuation' means the destination is adjacent to the source basic block on the bytecode.
cont: BranchMode,
mode: BranchMode,
}

pub(crate) fn conv(reg: SlotId) -> i32 {
Expand Down Expand Up @@ -708,26 +699,20 @@ impl Codegen {

// generate machine code for a main context
for (bbid, ir) in std::mem::take(&mut ctx.ir).into_iter() {
self.gen_asm(ir, store, &mut ctx, None);
// generate machine code for bridges
self.gen_asm(ir, store, &mut ctx, None, None);
// generate machine code for continue bridges
if let Some(bbid) = bbid
&& let Some((ir, exit)) = ctx.continue_bridges.remove(&bbid)
&& let Some((ir, exit)) = ctx.inline_bridges.remove(&bbid)
{
self.gen_asm(ir, store, &mut ctx, None);
let exit = ctx.get_bb_label(exit);
let exit = ctx.resolve_label(&mut self.jit, exit);
monoasm! { &mut self.jit,
jmp exit;
}
self.gen_asm(ir, store, &mut ctx, None, exit);
}
}

// generate machine code for bridges
for (ir, entry, exit) in std::mem::take(&mut ctx.bridges) {
for (ir, entry, exit) in std::mem::take(&mut ctx.outline_bridges) {
let entry = ctx.resolve_label(&mut self.jit, entry);
self.gen_asm(ir, store, &mut ctx, Some((entry, exit)));
self.gen_asm(ir, store, &mut ctx, Some(entry), Some(exit));
}
assert!(ctx.continuation_bridge.is_none());

self.jit.finalize();

Expand Down
13 changes: 9 additions & 4 deletions monoruby/src/compiler/jitgen/asmir.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -702,7 +702,6 @@ pub(super) enum AsmInst {
Raise,
MethodRet(BytecodePtr),
EnsureEnd,
Br(JitLabel),
///
/// Conditional branch
///
Expand Down Expand Up @@ -1376,7 +1375,8 @@ impl Codegen {
ir: AsmIr,
store: &Store,
ctx: &mut JitContext,
entry_exit: Option<(DestLabel, BasicBlockId)>,
entry: Option<DestLabel>,
exit: Option<BasicBlockId>,
) {
let mut side_exits = SideExitLabels::new();
for side_exit in ir.side_exit {
Expand All @@ -1396,8 +1396,11 @@ impl Codegen {
}
}

if let Some((entry, _)) = entry_exit {
if entry.is_some() && exit.is_some() {
self.jit.select_page(1);
}

if let Some(entry) = entry {
self.jit.bind_label(entry);
}

Expand All @@ -1410,12 +1413,14 @@ impl Codegen {
self.compile_asmir(store, ctx, &side_exits, inst);
}

if let Some((_, exit)) = entry_exit {
if let Some(exit) = exit {
let exit = ctx.get_bb_label(exit);
let exit = ctx.resolve_label(&mut self.jit, exit);
monoasm! { &mut self.jit,
jmp exit;
}
}
if entry.is_some() && exit.is_some() {
self.jit.select_page(0);
}
}
Expand Down
6 changes: 0 additions & 6 deletions monoruby/src/compiler/jitgen/asmir/compile.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -286,12 +286,6 @@ impl Codegen {
jne raise;
};
}
AsmInst::Br(dest) => {
let dest = ctx.resolve_label(&mut self.jit, dest);
monoasm!( &mut self.jit,
jmp dest;
);
}
AsmInst::CondBr(brkind, dest) => {
let branch_dest = ctx.resolve_label(&mut self.jit, dest);
self.cond_br(branch_dest, brkind);
Expand Down
62 changes: 21 additions & 41 deletions monoruby/src/compiler/jitgen/compile.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -43,14 +43,12 @@ impl JitContext {
eprintln!(" new_branch_init: {}->{}", BcIndex(0), start_pos);

let bb_begin = func.bb_info.get_bb_id(start_pos);
let branch_dest = self.label();
self.branch_map.insert(
bb_begin,
vec![BranchEntry {
src_bb: BasicBlockId(0),
bbctx,
branch_dest,
cont: BranchMode::Continue { dest: branch_dest },
mode: BranchMode::Continue,
}],
);

Expand Down Expand Up @@ -128,14 +126,12 @@ impl JitContext {
let mut liveness = Liveness::new(self.total_reg_num());

let bbctx = BBContext::new(&ctx);
let branch_dest = ctx.label();
ctx.branch_map.insert(
loop_start,
vec![BranchEntry {
src_bb: BasicBlockId(0),
bbctx,
branch_dest,
cont: BranchMode::Continue { dest: branch_dest },
mode: BranchMode::Continue,
}],
);

Expand Down Expand Up @@ -203,18 +199,15 @@ impl JitContext {
) -> Option<BBContext> {
if let Some(bb) = self.target_ctx.remove(&bbid) {
Some(bb)
} else if let Some(bb) = self.incoming_context(ir, func, bbid) {
Some(bb)
} else {
None
self.incoming_context(ir, func, bbid)
}
}

fn prepare_next(&mut self, ir: &mut AsmIr, bbctx: BBContext, func: &ISeqInfo, end: BcIndex) {
let next_idx = end + 1;
if let Some(next_bbid) = func.bb_info.is_bb_head(next_idx) {
let label = self.label();
self.new_continue(func, end, next_bbid, bbctx, label);
self.new_continue(func, end, next_bbid, bbctx);
if let Some(target_ctx) = self.incoming_context(ir, func, next_bbid) {
assert!(self.target_ctx.insert(next_bbid, target_ctx).is_none());
}
Expand Down Expand Up @@ -503,43 +496,43 @@ impl JitContext {
TraceIr::FCmpBr {
kind,
info,
dest,
dest_bb,
brkind,
} => {
let index = bc_pos + 1;
let branch_dest = self.label();
let src_idx = bc_pos + 1;
let dest = self.label();
let mode = bbctx.fmode(ir, info);
bbctx.discard(info.dst);
bbctx.clear_above_next_sp();
ir.float_cmp_br(mode, kind, brkind, branch_dest);
self.new_side_branch(func, index, dest, bbctx.clone(), branch_dest);
ir.float_cmp_br(mode, kind, brkind, dest);
self.new_side_branch(func, src_idx, dest_bb, bbctx.clone(), dest);
}
TraceIr::ICmpBr {
kind,
dst: _,
mode,
dest,
dest_bb,
brkind,
} => {
let index = bc_pos + 1;
let branch_dest = self.label();
bbctx.gen_cmpbr_integer(ir, kind, mode, brkind, branch_dest);
self.new_side_branch(func, index, dest, bbctx.clone(), branch_dest);
let src_idx = bc_pos + 1;
let dest = self.label();
bbctx.gen_cmpbr_integer(ir, kind, mode, brkind, dest);
self.new_side_branch(func, src_idx, dest_bb, bbctx.clone(), dest);
}
TraceIr::GCmpBr {
kind,
info,
dest,
dest_bb,
brkind,
} => {
let recv_class = info.lhs_class;
let name = Self::cmpkind_to_id(kind);
if let Some(fid) = self.jit_check_method(store, recv_class, name) {
match self.compile_binop_call(bbctx, ir, store, fid, info) {
CompileResult::Continue => {
let index = bc_pos + 1;
let src_idx = bc_pos + 1;
bbctx.unset_class_version_guard();
self.gen_cond_br(bbctx, ir, func, index, dest, brkind);
self.gen_cond_br(bbctx, ir, func, src_idx, dest_bb, brkind);
//let branch_dest = self.label();
//ir.push(AsmInst::CondBr(brkind, branch_dest));
//self.new_branch(func, index, dest, bbctx.clone(), branch_dest);
Expand Down Expand Up @@ -763,20 +756,20 @@ impl JitContext {
ir.push(AsmInst::EnsureEnd);
}
TraceIr::Br(dest_idx) => {
self.compile_branch(ir, bbctx, func, bc_pos, dest_idx);
self.new_branch(func, bc_pos, dest_idx, bbctx.clone());
return CompileResult::Branch;
}
TraceIr::CondBr(cond_, dest_idx, false, brkind) => {
if bbctx.is_truthy(cond_) {
if brkind == BrKind::BrIf {
self.compile_branch(ir, bbctx, func, bc_pos, dest_idx);
self.new_branch(func, bc_pos, dest_idx, bbctx.clone());
return CompileResult::Branch;
} else {
return CompileResult::Continue;
}
} else if bbctx.is_falsy(cond_) {
if brkind == BrKind::BrIfNot {
self.compile_branch(ir, bbctx, func, bc_pos, dest_idx);
self.new_branch(func, bc_pos, dest_idx, bbctx.clone());
return CompileResult::Branch;
} else {
return CompileResult::Continue;
Expand All @@ -788,7 +781,7 @@ impl JitContext {
}
TraceIr::NilBr(cond_, dest_idx) => {
if bbctx.is_nil(cond_) {
self.compile_branch(ir, bbctx, func, bc_pos, dest_idx);
self.new_branch(func, bc_pos, dest_idx, bbctx.clone());
return CompileResult::Branch;
} else if bbctx.is_not_nil(cond_) {
} else {
Expand Down Expand Up @@ -852,19 +845,6 @@ impl JitContext {
CmpKind::Cmp => IdentId::_CMP,
}
}

fn compile_branch(
&mut self,
ir: &mut AsmIr,
bbctx: &mut BBContext,
func: &ISeqInfo,
bc_pos: BcIndex,
dest: BasicBlockId,
) {
let branch_dest = self.label();
ir.push(AsmInst::Br(branch_dest));
self.new_branch(func, bc_pos, dest, bbctx.clone(), branch_dest);
}
}

#[cfg(feature = "emit-cfg")]
Expand Down
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