Add images to README and fix typos

Author: bonnee

README.md

@@ -9,24 +9,58 @@
                                           `.__.-.__.'
 
 ```
-
 ----
 
-DLX ISA, RISC microprocessor, VHDL implementation
+### Author Note
+> I don't like this folder structure but it was imposed on us to keep the project "tidier" and simpler to recognize the hierarchy from. To be honest the constraint is understandable but it's still awful to look at and use.
 
 ## Block Level Overview
 ![top_level](./doc/images/top_level_github.drawio.png)
-
+As can be seen in the block schema of the processor, data and instruction memories are placed outside the CPU.
+
+## Data-path
+The data-path is represented in black, the control unit and its signals are blue and the hazard unit is purple.
+![data-path](doc/images/datapath.jpg)
+
+## ALU
+The ALU features a Pentium 4 adder unit, a UltraSPARC T2 Shifter and Logic units and a behavioural comparator unit.
+![alu](doc/images/alu.jpg)
+
+### T2 Shifter
+The shifter unit is based on the SUN UltraSPARC T2 design, with a three-stage
+shifter implemented using masks shifted by varying amounts and combined to obtain
+the required operation. The implemented unit is able to perform left and right
+logical shifts and right arithmetical shifts.
+![t2 Shifter Unit](doc/images/shifter.jpg)
+#### Mask Generator
+The mask generator generates four masks, that contain the
+input A signal shifted by 8, 16, 24 and 32 bits respectively. The shift direction is
+dictated by the op signal (`00` for logical left shift, `01` for logical right shifts and
+`10` for arithmetical right shifts). An additional signal, msb, generates a fifth mask
+that is used for AMOUNT values greater than 31. The value of msb is `0` when a
+logical shift is being performed and is equals to the most-significant bit of A when
+an arithmetic shift is selected.
+#### Coarse Shift
+The coarse shift stage selects the coarse mask by considering the 30
+most-significant bits of the AMOUNT signal. If AMOUNT is bigger than 31, the
+coarse shift will select the msb mask.
+#### Fine Shift
+The fine shift will shift the selected coarse mask by the three least-
+significant digits of AMOUNT , completing the shift operation
+
+### T2 Logic Unit
+The T2 logic unit is able to perform five logical operations with just five NAND gates.
+![T2 Logic Unit](doc/images/logic.jpg)
 
 ## Dependencies
 - Questa Sim-64 10.7c
 - design compiler F-2011.09-SP3
 - Bash
-- Pearl
+- Perl
 
 ## How To Run An Assembly Program
 1) Write an Assembly program using the DLX isa found [here](./doc/isa.md)
-   1) The size of your program (lines of code), must be so that it culd be saved in the instruction memory. If your program exceeds this size the design will not compile, in such case change the value `C_IMEM_ADDR_W` in file `./src/000-common.core/000-DLX_PKG.vhd` accordingly.
+   1) The size of your program (lines of code), must be so that it could be saved in the instruction memory. If your program exceeds this size the design will not compile, in such case change the value `C_IMEM_ADDR_W` in file `./src/000-common.core/000-DLX_PKG.vhd` accordingly.
    2) If you need to address more then the default data-memory space change the variable 
    `C_DMEM_ADDR_W` in file `./src/000-common.core/000-DLX_PKG.vhd` accordingly. The compiler can't catch this error, the design will simulate your design but will truncate the data-memory-addresses to comply with its internal address space.
 
@@ -51,7 +85,7 @@ DLX ISA, RISC microprocessor, VHDL implementation
    ```
    To change the simulation time modify the line `run 212us` in `./sim/sim.do`
 
-5) The simulation will output the file `./sim/rf_dmemd.dump`. This file contains the content of the Register file (in order 0 to 31) and data memroy (in reverse order DATA_MEM_SIZE-1 downto 0). Check this file to see if your program is compliant with your behaviour (you obviously need to save the program state either in data memory of in the register file)
+5) The simulation will output the file `./sim/rf_dmemd.dump`. This file contains the content of the Register file (in order 0 to 31) and data memory (in reverse order `DATA_MEM_SIZE-1 downto 0`). Check this file to see if your program is compliant with your behaviour (you obviously need to save the program state either in data memory of in the register file)
 
 ## How To Syntesize The Design
 The design synthesized is only MELA without memories.  
@@ -76,11 +110,11 @@ Select the configuration and the desired clock-period in nanoseconds (can be a f
 Synthesis outputs will be in the `./syn` folder, respectively:
 - `./syn/reports` will contain timing, area and power reports
 - `./syn/netlists` will contain the synthesized netlist
-- `./syn/design_compiler_sdc` will contain the `sdc` file generated by design compiler for this syntesis run
+- `./syn/design_compiler_sdc` will contain the `sdc` file generated by design compiler for this synthesis run
 
 ## Place And Route
-Here some nice pictures. No description for this process because we didn't know what we where doing, just followin a recepy, but nice pics.  
-### Asic View
+Here some nice pictures. No description for this process because we didn't know what we where doing, just following a recipe, but nice pics.  
+### ASIC View
 |All metal layers                                                      | Transistor cells                                              |
 |----------------------------------------------------------------------|---------------------------------------------------------------|
 |![place_and_route](./doc/images/place_and_route.png)                  |![transistor_cells](./doc/images/transistor_cells_overview.png)|
@@ -93,7 +127,24 @@ Here some nice pictures. No description for this process because we didn't know
 ![alu_space](./doc/images/ss_alu.png)
 
 ## Notes 
-I don't like this folder strcuture but it was imposed on us to keep the project "tidier" and simpler to recognize the hierarchy from. 
-To be honest the constraint is understandable but it's still aweful to look at and use.
+I don't like this folder structure but it was imposed on us to keep the project "tidier" and simpler to recognize the hierarchy from. 
+To be honest the constraint is understandable but it's still awful to look at and use.
+
+## ALU
+MELA's ALU features a Pentium 4 adder unit, UltraSPARC T2 Shifter and Logic units, and a behavioural comparator. The ALU can be configured to have behavioural implementations of the aforementioned units.
+
+
+For more info about MELA's architecture, check out the [report](doc/report.pdf)
+
+## Nerd corner
+### Vim bindings
+Make sure the vim `PWD` is the root of the project
+```
+# compile the asm file open in the current buffer
+:nnoremap <F4> :!./scripts/assembler/assembler.sh % ./src/000-common.core/003-IMEM_INIT_FILE.txt<cr>
+# save all buffers and push to remote
+:nnoremap <F5> :wa<cr>:! rsync -hh -a --info=stats1,progress2 --partial /home/simone/Documents/00.PoliTO/1.2-MicroElectronic-Systems/DLX/ ms_polito:~/dlx_simone<cr>
+# compile on remote
+:nnoremap <F6> :! ssh ms_polito "cd ./dlx_simone; ./scripts/build.sh"<cr>
+```
 
-[MicroEletronics PoliTO]