align to schema overhaul

siliconcompiler · Jul 5, 2024 · 8e5a5e0 · 8e5a5e0
1 parent 42dbd4b
commit 8e5a5e0
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Showing 3 changed files with 3 additions and 7 deletions.
diff --git a/lambdapdk/freepdk45/__init__.py b/lambdapdk/freepdk45/__init__.py
@@ -53,8 +53,7 @@ def setup(chip):
     pdk.set('pdk', process, 'stackup', stackup)
     pdk.set('pdk', process, 'wafersize', wafersize)
     pdk.set('pdk', process, 'edgemargin', edgemargin)
-    pdk.set('pdk', process, 'hscribe', hscribe)
-    pdk.set('pdk', process, 'vscribe', vscribe)
+    pdk.set('pdk', process, 'scribe', (hscribe, vscribe))
     pdk.set('pdk', process, 'd0', d0)
 
     # APR Setup

diff --git a/lambdapdk/gf180/libs/gf180mcu.py b/lambdapdk/gf180/libs/gf180mcu.py
@@ -62,13 +62,11 @@ def setup(chip):
         for size in (1, 2, 3, 4, 8, 12, 16, 20):
             lib.add('asic', 'cells', 'clkbuf', f'gf180mcu_fd_sc_mcu{libtype}5v0__clkbuf_{size}')
 
-        # hold / delay cells
+        # hold cells
         for variant in ('a', 'b', 'c', 'd'):
             for size in (1, 2, 4):
                 lib.add('asic', 'cells', 'hold',
                         f'gf180mcu_fd_sc_mcu{libtype}5v0__dly{variant}_{size}')
-                lib.add('asic', 'cells', 'delay',
-                        f'gf180mcu_fd_sc_mcu{libtype}5v0__dly{variant}_{size}')
 
         # Decoupling
         for size in (4, 8, 16, 32, 64):

diff --git a/lambdapdk/sky130/__init__.py b/lambdapdk/sky130/__init__.py
@@ -61,8 +61,7 @@ def setup(chip):
     pdk.set('pdk', process, 'stackup', stackup)
     pdk.set('pdk', process, 'wafersize', wafersize)
     pdk.set('pdk', process, 'edgemargin', edgemargin)
-    pdk.set('pdk', process, 'hscribe', hscribe)
-    pdk.set('pdk', process, 'vscribe', vscribe)
+    pdk.set('pdk', process, 'scribe', (hscribe, vscribe))
 
     # APR Setup
     # TODO: remove libtype